1
Rafael C Camarota, Frederick C Furtek, Walford W Ho, Edward H Browder: Programmable logic cell and array. Concurrent Logic, Pennie & Edmonds, September 1, 1992: US05144166 (334 worldwide citation)

A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four near ...


2
Walford W Ho, Chao Chiang Chen, Yuk Y Yang: Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array. Intelligent Logic Systems, Phong K Fenwick & West Truong, October 3, 1995: US05455525 (329 worldwide citation)

A structured logic array is divided into hierarchical levels. At a highest level (the chip level), blocks are interconnected by a system of chip busses. A block interface couples each block to the chip bus system to allow the blocks to communicate with each other. At a lower level, each block includ ...


3
Rafael C Camarota, Frederick C Furtek, Walford W Ho, Edward H Browder: Programmable logic cell and array with bus repeaters. Concurrent Logic, Pennie & Edmonds, June 8, 1993: US05218240 (83 worldwide citation)

A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four near ...