1
Wagdi W Abadeer, Kiran V Chatty, Robert J Gauthier Jr, Jed H Rankin, Yun Shi, William R Tonti: Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures. International Business Machines Corporation, Wood Herron & Evans, September 7, 2010: US07790524 (72 worldwide citation)

Device and design structures for memory cells in a non-volatile random access memory (NVRAM) and methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes. The device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, in ...


2
Wagdi W Abadeer, Badih El Kareh, Wayne F Ellis, Duane E Galbi, Nathan R Hiltebeitel, William R Tonti, Josef S Watts: Low voltage programmable storage element. International Business Machines Corporation, Sughrue Mion Zinn Macpeak & Seas, August 2, 1994: US05334880 (69 worldwide citation)

A programmable storage element for redundancy-programming includes a programmable antifuse circuit, which includes a plurality of first resistors and a switching circuit for coupling the first resistors in series in response to a plurality of first control signals and for coupling the first resistor ...


3
Wagdi W Abadeer, Jeffrey S Brown, David M Fried, Robert J Gauthier Jr, Edward J Nowak, Jed H Rankin, William R Tonti: Concurrent Fin-FET and thick-body device fabrication. International Business Machines Corporation, Schmeiser Olsen & Watts, Richard M Kotulak, January 16, 2007: US07163851 (67 worldwide citation)

The present invention provides methods for fabrication of fin-type field effect transistors (FinFETs) and thick-body devices on the same chip using common masks and steps to achieve greater efficiency than prior methods. The reduction in the number of masks and steps is achieved by using common mask ...


4
Wagdi W Abadeer, Kiran V Chatty, Robert J Gauthier Jr, Jed H Rankin, Yun Shi, William R Tonti: Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures. International Business Machines Corporation, Wood Herron & Evans, September 7, 2010: US07790543 (64 worldwide citation)

Device structures for a metal-oxide-semiconductor field effect transistor (MOSFET) that is suitable for operation at relatively high voltages and methods of forming same. The MOSFET, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a channel in a semiconductor body that i ...


5
Wagdi W Abadeer, Jeffrey S Brown, Kiran V Chatty, Robert J Gauthler Jr, Jed H Rankin, William R Tonti: Method and structure to process thick and thin fins and variable fin to fin spacing. International Business Machines Corporation, Gibb I P Law Firm, July 27, 2010: US07763531 (44 worldwide citation)

The disclosure describes an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing ...


6
Wagdi W Abadeer, Jeffrey S Brown, Robert J Gauthier Jr, Jed H Rankin, William R Tonti: High voltage N-LDMOS transistors having shallow trench isolation region. International Business Machines Corporation, McGinn & Gibb PLLC, Mark F Chadurjian Esq, April 5, 2005: US06876035 (41 worldwide citation)

A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between th ...


7
Wagdi W Abadeer, Jeffrey S Brown, Kiran V Chatty, Robert J Gauthier Jr, Jed H Rankin, William R Tonti: Method and structure to process thick and thin fins and variable fin to fin spacing. International Business Machines Corporation, Gibb & Rahman, William D Sabo Esq, November 27, 2007: US07301210 (34 worldwide citation)

Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are control ...


8
Jed H Rankin, Wagdi W Abadeer, Jeffrey S Brown, William R Tonti: Integrated antifuse structure for FINFET and CMOS devices. International Business Machines Corporation, H Daniel Schnurmann, August 8, 2006: US07087499 (32 worldwide citation)

A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of co ...


9
Wagdi W Abadeer, Badih El Kareh, Wayne F Ellis, Duane E Galbi, Nathan R Hiltebeitel, William R Tonti, Josef S Watts: Low voltage programmable storage element. International Business Machines Corporation, Richard C Turner, Raymond H J Powell Jr, Sughrue Mion Zinn Macpeak & Seas, May 23, 1995: US05418738 (29 worldwide citation)

A programmable storage element for redundancy-programing includes a programmable antifuse circuit, which includes a plurality of first resistors and a switching circuit for coupling the first resistors in series in response to a plurality of first control signals and for coupling the first resistors ...


10
Wagdi W Abadeer, Eric Adler, Jeffrey S Brown, Robert J Gauthier Jr, Jonathan M McKenna, Jed H Rankin, Edward W Sengle, William R Tonti: Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure. International Business Machines Corporation, Mark F Chadurjian, Schmeiser Olsen & Watts, September 23, 2003: US06624031 (28 worldwide citation)

A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from th ...