1
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logic cell array and bus system. Pact XPP Technologies, Kenyon & Kenyon, September 29, 2009: US07595659 (46 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


2
Martin Vorbach, Jürgen Becker, Markus Weinhardt, Volker Baumgarte, Frank May: Data processing method and device. Kenyon & Kenyon, April 10, 2012: US08156284 (31 worldwide citation)

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurabl ...


3
Martin Vorbach, Volker Baumgarte, Gerd Ehlers, Frank May, Armin Nückel: Pipeline configuration unit protocols and communication. PACT XPP Technologies, Kenyon & Kenyon, February 21, 2006: US07003660 (22 worldwide citation)

An example method of controlling a data processing system having a cellular structure. The method includes transmitting a first configuration word to a first processing unit in the cellular structure. The method also includes processing data with the first processing unit in accordance with the firs ...


4
Martin Vorbach, Volker Baumgarte: Methods and devices for treating and processing data. Pact XPP Technologies, Kenyon & Kenyon, October 28, 2008: US07444531 (20 worldwide citation)

A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselect ...


5
Martin Vorbach, Volker Baumgarte: Methods and devices for treating and processing data. Kenyon & Kenyon, January 17, 2012: US08099618 (8 worldwide citation)

A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselect ...


6
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logical cell array and bus system. PACT XPP TECHNOLOGIES, Edward P Heller III, June 2, 2015: US09047440 (5 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


7
Martin Vorbach, Volker Baumgarte, Gerd Ehlers, Frank May, Armin Nückel: Pipeline configuration protocol and configuration unit communication. Kenyon & Kenyon, October 30, 2012: US08301872 (4 worldwide citation)

An example method of controlling a data processing system having a cellular structure. The method includes transmitting a first configuration word to a first processing unit in the cellular structure. The method also includes processing data with the first processing unit in accordance with the firs ...


8
Martin Vorbach, Jürgen Becker, Markus Weinhardt, Volker Baumgarte, Frank May: Data processing system having integrated pipelined array data processor. PACT XPP TECHNOLOGIES, Edward P Heller III, October 27, 2015: US09170812 (4 worldwide citation)

A data processing system having a data processing core and integrated pipelined array data processor and a buffer for storing list of algorithms for processing by the pipelined array data processor.


9
Martin Vorbach, Volker Baumgarte: Reconfigurable general purpose processor having time restricted configurations. Kenyon & Kenyon, October 2, 2012: US08281108 (3 worldwide citation)

A processor includes a reconfigurable field of data processing cells. A register is provided where the register has a data stream memory designed to store a data stream and/or parts thereon. The register may be a RAM PAE.


10
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logic cell array and bus system. Bechen PLLC, June 25, 2013: US08471593 (2 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...