1
John Cocke, Gregory F Grohoski, Vojin G Oklobdzija: Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers. International Business Machines Corporation, Jack M Arnold, February 12, 1991: US04992938 (165 worldwide citation)

A floating point instruction control mechanism which processes loads and stores in parallel with arithmetic instructions. This results from register renaming, which removes output dependencies in the instruction control mechanism and allows computations aliased to the same register to proceed in par ...


2
Vojin G Oklobdzija, Daniel T Ling: Instruction prefetch buffer control. International Business Machines, C Lamont Whitham, December 22, 1987: US04714994 (105 worldwide citation)

An instruction prefetch buffer control (20) is provided for an instruction prefetch buffer array (10) which stores the code for a number of instructions that have already been executed as well as the code for a number of instructions yet to be executed. The instruction prefetch buffer control includ ...


3
Farzad Chehrazi, Vojin G Oklobdzija, Aamir A Farooqui: High performance universal multiplier circuit. Sony Corporation of Japan, Sony Electronics, Wagner Murabito & Hao, March 5, 2002: US06353843 (64 worldwide citation)

A partitioned multiplier circuit which is designed for high speed operations. The multiplier of the present invention can perform one 32×32 bit multiplication, two 16×16 bit multiplications (simultaneously) or four 8×8 bit multiplications (simultaneously) depending on input partitioning signals. The ...


4
Daniel T Ling, Vojin G Oklobdzija, Norman Raver: Consistent precharge circuit for cascode voltage switch logic. International Business Machines Corporation, Sughrue Mion Zinn Macpeak and Seas, October 13, 1987: US04700086 (52 worldwide citation)

A precharge circuit for a cascode voltage switch in which at the beginning of the precharge phase the output state is memorized and the output is isolated from the precharging points. Both the positive and negative ends of the discharge paths are precharged with the gates of the switches in all path ...


5
Rod G Fleck, Roger D Arnold, Bruce Holmer, Vojin G Oklobdzija, Eric Chesters: Data processing unit with hardware assisted context switching capability. Siemens Aktiengesellschaft, October 3, 2000: US06128641 (36 worldwide citation)

The present invention relates to a method of context switching from a first task to a second task in a data processing unit having a register file with a plurality of general purpose registers and a context switch register, a memory comprising a previous context save area and an unused context save ...


6
Farzad Chehrazi, Vojin G Oklobdzija: High performance pipelined data path for a media processor. Sony Corporation of Japan, Sony Electronics, Wagner Murabito & Hao, August 28, 2001: US06282556 (24 worldwide citation)

A pipelined data path architecture for use, in one embodiment, in a multimedia processor. The data path architecture requires a maximum of two execution pipestages to perform all instructions including wide data format multiply instructions and specially adapted multimedia instructions, such as the ...


7
Vojin G Oklobdzija: Register selection mechanism and organization of an instruction prefetch buffer. International Business Machines, Whitham & Marhoefer, July 11, 1989: US04847759 (22 worldwide citation)

A register selection mechanism for an instruction prefetch buffer which allows instructions having different lengths to be accessed on the instruction boundaries. The instruction prefetch buffer comprises a one-port-write, two-port-read array (10). Address generation and control logic (16) is respon ...


8
Aamir Alam Farooqui, Vojin G Oklobdzija, Farzad Chehrazi, Wei Jen Li, Andy W Yu: Partitioned shift right logic circuit having rounding support. Sony Corporation of Japan, Sony Electronics, Wagner Murabito & Hao, June 5, 2001: US06243728 (12 worldwide citation)

A partitioned shift right logic circuit that is programmable and contains rounding support. The circuit of the present invention accepts a 32-bit value and a shift amount and then performs a right shift operation on the 32-bits and automatically rounds the result(s). Signed or unsigned values can be ...


9
Vojin G Oklobdzija, Vladimir Stojanovic: Flip-flop. Hitachi America, Flehr Hohbach Test Albritton & Herbert, May 15, 2001: US06232810 (9 worldwide citation)

An improved SR latch has a two stages. A generation block generates Q and {overscore (Q)} signals from a set signal and a reset signal. The generation block also has an inactive state. A storage block receives the Q and {overscore (Q)} signals and maintains the Q signal and {overscore (Q)} signals a ...


10
Farzad Chehrazi, Vojin G Oklobdzija, Aamir Alam Farooqui: Multiplier circuit having an optimized booth encoder/selector. Sony Corporation of Japan, Sony Electronics, Wagner Murabito & Hao, October 9, 2001: US06301599 (9 worldwide citation)

An improved Booth encoder/selector circuit having an optimized critical path. The Booth encoder has a number of inverters coupled to several of the input multiplier bits. The inverted/non-inverted multiplier bits are then fed as inputs to NAND gates as well as a series of pass gates. The outputs of ...