1
Taber H Smith, Vikas Mehrotra, David White: Characterization and reduction of variation for integrated circuits. Cadence Design Systems, Bingham McCutchen, June 3, 2008: US07383521 (259 worldwide citation)

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.


2
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Praesagus, Bingham McCutchen, October 17, 2006: US07124386 (244 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


3
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Praesagus, Fish & Richardson P C, December 19, 2006: US07152215 (231 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


4
Taber H Smith, Vikas Mehrotra, David White: Use of models in integrated circuit fabrication. Cadence Design Systems, Bingham McCutchen, April 15, 2008: US07360179 (186 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


5
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Cadence Design Systems, Bingham McCutchen, May 27, 2008: US07380220 (25 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


6
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Cadence Design Systems, Bingham McCutchen, April 8, 2008: US07356783 (25 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


7
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Cadence Design Systems, Bingham McCutchen, July 1, 2008: US07393755 (25 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


8
Taber H Smith, Vikas Mehrotra, David White: Characterization and reduction of variation for integrated circuits. Cadence Design Systems, Vista IP Law Group, August 16, 2011: US08001516 (23 worldwide citation)

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.


9
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Cadence Design Systems, Bingham McCutchen, April 22, 2008: US07363598 (23 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


10
Taber H Smith, Vikas Mehrotra, David White: Methods and systems for implementing dummy fill for integrated circuits. Cadence Design Systems, Vista IP Law Group, July 13, 2010: US07757195 (7 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...



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