1
Tsu Jae King, Victor Moroz: Segmented channel MOS transistor. Synopsys, Bever Hoffman & Harms, Jeanette S Harms, July 24, 2007: US07247887 (327 worldwide citation)

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repe ...


2
Tsu Jae King, Victor Moroz: Integrated circuit on corrugated substrate. Synopsys, Bever Hoffman & Harms, Jeanette S Harms, March 13, 2007: US07190050 (250 worldwide citation)

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repe ...


3
Tsu Jae King, Victor Moroz: Integrated circuit on corrugated substrate. Synopsys, Bever Hoffman & Harms, Jeanette S Harms, May 5, 2009: US07528465 (229 worldwide citation)

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repe ...


4
Tsu Jae King, Victor Moroz: Method of IC production using corrugated substrate. Synopsys, Bever Hoffman & Harms, Jeanette S Harms, September 4, 2007: US07265008 (220 worldwide citation)

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repe ...


5
Tsu Jae King, Victor Moroz: Methods of designing an integrated circuit on corrugated substrate. Synopsys, Bever Hoffman & Harms, Jeanette S Harms, June 14, 2011: US07960232 (117 worldwide citation)

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repe ...


6
Victor Moroz, Xi Wei Lin, Mark Rubin: Method and apparatus for generating a layout for a transistor. Synopsys, Park Vaughan Fleming & Dowler, April 12, 2011: US07926018 (90 worldwide citation)

A system that generates a layout for a transistor is presented. During operation, the system receives a transistor library which includes operating characteristics of fabricated transistors correlated to transistor gate shapes. The system also receives one or more desired operating characteristics f ...


7
Xi Wei Lin, Dipankar Pramanik, Victor Moroz: Managing integrated circuit stress using dummy diffusion regions. Synopsys, Warren S Wolfeld, Haynes Beffel & Wolfeld, January 27, 2009: US07484198 (31 worldwide citation)

Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirabl ...


8
Xi Wei Lin, Victor Moroz, Dipankar Pramanik: Method of correlating silicon stress to device instance parameters for circuit simulation. Synopsys, Warren S Wolfeld, Haynes Beffel & Wolfeld, June 2, 2009: US07542891 (25 worldwide citation)

Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor ...


9
Victor Moroz, Tsu Jae King Liu: Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layers. Synopsys, Bever Hoffman & Harms, Jeanette S Harms, May 10, 2011: US07939862 (20 worldwide citation)

Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping la ...


10
Jamil Kawa, Victor Moroz, Deepak Sherlekar: N-channel and P-channel finFET cell architecture with inter-block insulator. Synopsys, Haynes Beffel & Wolfeld, October 15, 2013: US08561003 (17 worldwide citation)

A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer incl ...