1
Victor M Da Costa, Patrick A O Connell: Integrated thin film transistor electrographic writing head. Xerox Corporation, Lisa M Yamonaco, August 17, 1993: US05237346 (47 worldwide citation)

An integrated thin film electrographic writing head. The writing head has integrated therein a plurality of marking electrodes or nibs arranged in a linear array for writing onto a medium, and a plurality of high voltage driving circuits for driving the nibs. The write head also includes a plurality ...


2
Gyudong Kim, Victor M Da Costa, Bruce Kim, David D Lee, Russel A Martin, Seung Ho Hwang: Methods and systems for TMDS encryption. Silicon Image, Perkins Coie, March 22, 2005: US06870930 (18 worldwide citation)

The present invention is directed to systems and methods for protecting digital content during transmission. One version of the invention provides a method for encryption in a high-speed digital video transmission system that includes the steps of: a) performing transition controlled encoding of a f ...


3
Victor M Da Costa: Space charge current limited shunt in a cascode circuit for HVTFT devices. Xerox Corporation, Serge Abend, December 17, 1991: US05073723 (18 worldwide citation)

A cascode circuit for switching a high voltage thin film transistor substantially over its entire high voltage range, comprising a leaky low voltage thin film transistor connected in series with the high voltage thin film transistor, the transistors being connected between a source of high potential ...


4
Victor M Da Costa: System and method for controlling an active matrix display. Silicon Image, Fenwick & West, August 8, 2000: US06100879 (16 worldwide citation)

A smart controller chip for controlling an active matrix display. Within the controller chip, circuitry for generating analog reference levels is incorporated alongside circuitry for generating digital timing and control signals. The combination of D/A analog circuitry and standard digital logic mak ...


5
Victor M Da Costa: Parallel multi-phased a-Si shift register for fast addressing of an a-Si array. Xerox Corporation, Lisa M Yamonaco, November 24, 1992: US05166960 (10 worldwide citation)

An improved shift register assembly having an integrated multi-phased dynamic shift register with a corresponding multi-phased driving buffer for addressing elements of an array. The shift register and buffer combination is used to select segments on the array having a common select line thus reduci ...


6
Stephen J Keating, Russel A Martin, Victor M Da Costa, Gyudong Kim: Digital display jitter correction apparatus and method. Silicon Image, Perkins Coie, November 1, 2005: US06961095 (3 worldwide citation)

A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal a ...


7
Stephen J Keating, Russel Martin, Victor M Da Costa, Gyudong Kim: Digital display jitter correction apparatus and method. Silicon Image, Perkins Coie, July 7, 2009: US07557863 (2 worldwide citation)

A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal a ...


8
Victor M Da Costa: Leaky low voltage thin film transistor. Xerox Corporation, April 14, 1992: US05105246 (1 worldwide citation)

A leaky thin film transistor including a charge transport layer, source and drain electrodes located adjacent to the charge transport layer, a gate electrode spaced from the charge transport layer by a gate dielectric layer, the gate electrode defining a gated portion of the charge transport layer e ...


9
Stephen J Keating, Russel A Martin, Victor M Da Costa, Gyudong Kim: Digital display jitter correction apparatus and method. Fenwick & West, April 25, 2002: US20020048336-A1

A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal a ...


10
Stephen J Keating, Russel A Martin, Victor M Da Costa, Gyudong Kim: Digital display jitter correction apparatus and method. Perkins Coie, March 16, 2006: US20060055822-A1

A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal a ...