1
Ravi Kumar Arimilli, Jerry Don Lewis, Vicente Enrique Chung, Jody Bern Joyner: Multiprocessor data processing system having scalable data interconnect and data routing mechanism. International Business Machines Corporation, Casimer K Salys, Dillon & Yudell, December 11, 2007: US07308558 (28 worldwide citation)

The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a data processing sys ...


2
Vicente Enrique Chung, Guy Lynn Guthrie, William John Starke, Jeffrey Adam Stuecheli: System bus structure for large L2 cache array topology with different latency domains. International Business Machines Corporation, Diana R Gerhardt, Jack V Musgrove, December 23, 2008: US07469318 (25 worldwide citation)

A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a ...


3
Ravi Kumar Arimilli, Vicente Enrique Chung, Warren Edward Maule: Method and apparatus for high performance transmission of ordered packets on a bus within a data processing system. International Business Machines Corporation, Volel Emile, Bracewell & Patterson L, June 17, 2003: US06581116 (15 worldwide citation)

A method for transmitting ordered packets on a bus within a data processing system is disclosed. A data processing system includes a bus connected between a bus master and a bus slave. The bus master consecutively issues multiple packets, such as command packets, to the bus slave on the bus. The pac ...


4
Jody Bern Joyner, Ravi Kumar Arimilli, Jerry Don Lewis, Vicente Enrique Chung: Robust system bus recovery. International Business Machines Corpoation, Casimer K Salys, Dillon & Yudell, March 8, 2005: US06865695 (10 worldwide citation)

A computer system of a number of processing nodes operate either in a loop configuration or off of a common bus with high speed, high performance wide bandwidth characteristics. The processing nodes in the system are also interconnected by a separate narrow bandwidth, low frequency recovery bus. Whe ...


5
Ravi Kumar Arimilli, Vicente Enrique Chung, Guy Lynn Guthrie, Jody Bern Joyner: System bus read address operations with data ordering preference hint bits for vertical caches. International Business Machines Corporation, Casimer K Salys, Bracewell & Patterson L, March 19, 2002: US06360297 (10 worldwide citation)

A method for preferentially ordering the retrieval of data from a cache line of a cache within a vertical cache configuration. The method includes the steps of first encoding a set of bits with a processor-preferred order of data retrieval based on the cache configuration. The set of bits is then se ...


6
Ravi Kumar Arimilli, Vicente Enrique Chung, Guy Lynn Guthrie, Jody Bern Joyner: System bus read address operations with data ordering preference hint bits. International Business Machines Corporation, Casimer K Salys, Bracewell & Patterson L, February 19, 2002: US06349360 (4 worldwide citation)

A method for preferentially ordering the retrieval of data from a system component, such as a cache line of a cache. The method includes the steps of first encoding a set of bits with a processor-preferred order of data retrieval. In the cache embodiment, the set of bits is then sent along with the ...


7
Ravi Kumar Arimilli, Vicente Enrique Chung, Guy Lynn Guthrie, Jody Bern Joyner: System bus read data transfers with bus utilization based data ordering. International Business Machines Corporation, Casimer K Salys, Bracewell & Patterson L, March 18, 2003: US06535957 (4 worldwide citation)

A method for selecting an order of data transmittal based on system bus utilization of a data processing system. The method comprises the steps of coupling system components to a processor within the data processing system to effectuate data transfer, dynamically determining based on current system ...


8
Ravi Kumar Arimilli, Vicente Enrique Chung, Jody Bern Joyner, Jerry Don Lewis: Data processing system with backplane and processor books configurable to support both technical and commercial workloads. International Business Machines Corporation, Casimer K Salys, Dillon & Yudell, April 28, 2009: US07526631 (3 worldwide citation)

A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with external connector bus ...


9
Ravi Kumar Arimilli, Vicente Enrique Chung, Warren Edward Maule: Error recovery mechanism for a high-performance interconnect. International Business Machines Corporation, Volel Emile, November 26, 2002: US06487679 (3 worldwide citation)

An error recovery mechanism for an interconnect is disclosed. A data processing system includes a bus connected between a bus master and a bus slave. In response to a parity error occurring on the bus, the bus slave issues a bus parity error response to the bus master via the bus. After waiting for ...


10
Ravi Kumar Arimilli, Vicente Enrique Chung, Guy Lynn Guthrie, Jody Bern Joyner: System bus read data transfers with data ordering control bits. International Business Machines Corporation, Casimer K Salys, Dillon & Yudell, March 29, 2005: US06874063 (2 worldwide citation)

A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to transmit data to ...