1
Valery M Dubin, Yosi Schacham Diamand, Bin Zhao, Prahalad K Vasudev, Chiu H Ting: Use of cobalt tungsten phosphide as a barrier material for copper metallization. Cornell Research Foundation, Sematech, Intel Corporation, William W Kidd, December 9, 1997: US05695810 (447 worldwide citation)

A technique for electrolessly depositing a CoWP barrier material on to copper and electrolessly depositing copper onto a CoWP barrier material to prevent copper diffusion when forming layers and/or structures on a semiconductor wafer.


2
Bin Zhao, Prahalad K Vasudev, Valery M Dubin, Yosef Shacham Diamand, Chiu H Ting: Selective electroless copper deposited interconnect plugs for ULSI applications. Sematech, Kidd & Booth, October 7, 1997: US05674787 (425 worldwide citation)

A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal l ...


3
Yosef Schacham Diamand, Valery M Dubin, Chiu H Ting, Bin Zhao, Prahalad K Vasudev, Melvin Desilva: Protected encapsulation of catalytic layer for electroless copper interconnect. Cornell Research Foundation, Intel Corporation, Sematech, October 20, 1998: US05824599 (305 worldwide citation)

A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum ...


4
Valery M Dubin, Yosef Shacham Diamand, Chiu H Ting, Bin Zhao, Prahalad K Vasudev: Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications. Cornell Research Foundation, Intel Corporation, Sematech, April 6, 1999: US05891513 (269 worldwide citation)

A method of utilizing electroless copper deposition to form interconnects on a semiconductor wafer. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is blanket deposited. Then, a contact displacement technique is used to form a thin acti ...


5
Valery M Dubin: Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure. Advanced Micro Devices, Monica H Choi, June 20, 2000: US06077780 (193 worldwide citation)

A method for filling, with a conductive material, a high aspect ratio opening such as a via hole or a trench opening within an integrated circuit minimizes the formation of voids and seams. This conductive material such as copper which fills the high aspect ratio opening is amenable for fine line me ...


6
Yosi Shacham Diamand, Valery M Dubin, Chiu H Ting, Bin Zhao, Prahalad K Vasudev: Electroless deposition equipment or apparatus and method of performing electroless deposition. Cornell Research Foundation, Sematech, Intel Corporation, November 3, 1998: US05830805 (181 worldwide citation)

An electroless deposition apparatus and a method of electroless deposition that uses a single process chamber for performing multiple processes by moving through the process chamber a variety of fluids one at a time in a sequential order.


7
Valery M Dubin, Dave W Jentz, Christopher Collazo Davila: Method of copper electroplating. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 13, 2002: US06432821 (70 worldwide citation)

An electroplating process for filling damascene structures on substrates, such as wafers having partially fabricated integrated circuits thereon, includes immersing a substrate, under bias, into a copper plating solution to eliminate thin seed layer dissolution and reduce copper oxide, an initiation ...


8
Ramanan V Chebiam, Valery M Dubin: Electroless plating bath composition and method of using. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 11, 2003: US06645567 (48 worldwide citation)

The present invention relates to a cobalt electroless plating bath composition and method of using it for microelectronic device fabrication. In one embodiment, the present invention relates to cobalt electroless plating in the fabrication of interconnect structures in semiconductor devices.


9
Valery M Dubin, Chin Chang Cheng, Makarem Hussein, Phi L Nguyen, Ruth A Brain: Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 25, 2005: US06958547 (36 worldwide citation)

Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interc ...


10
Valery M Dubin, Sridhar Balakrishnan, Mark Bohr: Designs and methods for conductive bumps. Intel Corporation, Fish & Richardson P C, October 2, 2007: US07276801 (33 worldwide citation)

Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. ...