1
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched. Townsend and Townsend and Crew, January 23, 1996: US05487156 (177 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


2
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition code. Hyundai Electronics America, Townsend and Townsend and Crew, April 29, 1997: US05625837 (120 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


3
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture supporting multiple speculative branching. Hyundai Electronics America, Townsend and Townsend and Crew, October 1, 1996: US05561776 (115 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


4
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture supporting multiple speculative branches and trap handling. Hyundai Electronics America, Townsend and Townsend and Crew, January 7, 1997: US05592636 (75 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


5
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture providing out-of-order execution. Hyundai Electronics America, Townsend and Townsend and Crew, May 6, 1997: US05627983 (74 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


6
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture providing speculative, out of order execution of instructions. Hyundai Electronics America, Pennie & Edmonds, January 13, 1998: US05708841 (70 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


7
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture providing speculative, out of order execution of instructions and trap handling. Hyundai Electronics America, Pennie & Edmonds, November 3, 1998: US05832293 (69 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


8
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture supporting speculative, out of order execution of instructions including multiple speculative branching. Hyundai Electronics America, Pennie & Edmonds, August 18, 1998: US05797025 (63 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


9
Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture providing for speculative execution of instructions with multiple predictive branching and handling of trap conditions. Hyundai Electronics America, Pennie & Edmonds, November 16, 1999: US05987588 (7 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...


10
Gary Allen Gibson, Valeri Popescu: Fine grain performance resource management of computer systems. VirtualMetrix, Mintz Levin Cohn Ferris Glovsky and Popeo P C, July 15, 2014: US08782653 (4 worldwide citation)

Execution of a plurality of tasks by a processor system are monitored. Based on this monitoring, tasks requiring adjustment of performance resources are identified by calculating at least one of a progress error or a progress limit error for each task. Thereafter, performance resources of the proces ...