1
Robert Michael Bunce, Christos John Georgiou, Valentina Salapura: Pipelined packet processing. International Business Machines Corporation, Richard A Henkler, Dillon & Yudell, December 28, 2004: US06836808 (152 worldwide citation)

A method and system for increasing the efficiency of packet processing within a packet protocol handler. In accordance with the method of the present invention packet processing tasks are performed on multiple processors or threads concurrently and in a pipelined fashion. Subsequent protocol packet ...


2
Matthias A Blumrich, Dong Chen, George Chiu, Thomas M Cipolla, Paul W Coteus, Alan G Gara, Mark E Giampapa, Shawn Hall, Rudolf A Haring, Philip Heidelberger, Gerard V Kopcsay, Martin Ohmacht, Valentina Salapura, Krishnan Sugavanam, Todd Takken: Ultrascalable petaflop parallel supercomputer. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Daniel P Morris Esq, July 20, 2010: US07761687 (63 worldwide citation)

A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple in ...


3
Christos J Georgiou, Victor L Gregurick, Valentina Salapura: Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph P Abate Esq, April 1, 2008: US07353362 (53 worldwide citation)

A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster wit ...


4
Christos J Georgiou, Victor L Gregurick, Indira Nair, Valentina Salapura: Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph P Abate Esq, August 12, 2008: US07412588 (51 worldwide citation)

A network processor includes a system-onchip (SoC) macro core and functions as a single chip protocol converter that receives packets generating according to a first protocol type and processes the packets to implement protocol conversion and generates converted packets of a second protocol type for ...


5
Michael Karl Gschwind, Valentina Salapura: Method and apparatus for software-assisted thermal management for electronic systems. International Business Machines Corporation, Satheesh K Karra, Harrington & Smith, September 20, 2005: US06948082 (35 worldwide citation)

In a computer system, a device for measuring power dissipation (e.g., using on-die thermal sensors) is linked to both a hardware-based thermal management solution and with a means for causing a notification event to software, so that, initially, the operating system software and/or the application s ...


6
Valentina Salapura, Christos J Georgiou: Packet preprocessing interface for multiprocessor network handler. International Business Machines Corporaiton, Whitham Curtis & Christofferson P C, William D Sabo, June 7, 2005: US06904040 (33 worldwide citation)

A network handler uses a DMA device to assign packets to network processors in accordance with a mapping function which classifies packets based on its content, e.g., bits in one or more header fields. Preferably, the mapping function is implemented as a hash function, which uses a predetermined num ...


7
Christos John Georgiou, Valentina Salapura: Dynamic reallocation of data stored in buffers based on packet size. International Business Machines Corporation, Richard Kotulak, Greenblum & Bernstein, February 21, 2006: US07003597 (27 worldwide citation)

A method and system is provided to efficiently manage memory in a network device that receives packets of variable size. The memory is allocated into portions whereby each portion, comprising multiple equally-sized buffers, receives packets of a particular size. One portion is used for smaller packe ...


8
Sameh Asaad, Ralph E Bellofatto, Michael A Blocksome, Matthias A Blumrich, Peter Boyle, Jose R Brunheroto, Dong Chen, Chen Yong Cher, George L Chiu, Norman Christ, Paul W Coteus, Kristan D Davis, Gabor J Dozsa, Alexandre E Eichenberger, Noel A Eisley, Matthew R Ellavsky, Kahn C Evans, Bruce M Fleischer, Thomas W Fox, Alan Gara, Mark E Giampapa, Thomas M Gooding, Michael K Gschwind, John A Gunnels, Shawn A Hall, Rudolf A Haring, Philip Heidelberger, Todd A Inglett, Brant L Knudson, Gerard V Kopcsay, Sameer Kumar, Amith R Mamidala, James A Marcella, Mark G Megerian, Douglas R Miller, Samuel J Miller, Adam J Muff, Michael B Mundy, John K O Brien, Kathryn M O Brien, Martin Ohmacht, Jeffrey J Parker, Ruth J Poole, Joseph D Ratterman, Valentina Salapura, David L Satterfield, Robert M Senger, Brian Smith, Burkhard Steinmacher Burow, William M Stockdell, Craig B Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E Takken, Barry M Trager, James L Van Oosten, Charles D Wait, Robert E Walkup, Alfred T Watson, Robert W Wisniewski, Peng Wu: Multi-petascale highly efficient parallel supercomputer. INTERNATIONAL BUSINESS MACHINES CORPORATION, Scully Scott Murphy & Presser P C, Daniel P Morris Esq, July 14, 2015: US09081501 (23 worldwide citation)

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that ena ...


9
Christos J Georgiou, Monty M Denneau, Valentina Salapura, Robert M Bunce: Programmable network protocol handler architecture. International Business Machines Corporation, Whitham Curtis Christofferson & Cook PC, Michael LaStrange, July 4, 2006: US07072970 (15 worldwide citation)

An architecture that achieves high speed performance in a network protocol handler combines parallelism and pipelining in multiple programmable processors, along with specialized front-end logic at the network interface that handles time critical protocol operations. The multiple processors are inte ...


10
Michael Karl Gschwind, Kathryn M O Brien, John Kevin O Brien, Valentina Salapura: Method and apparatus for enabling access to global data by a plurality of codes in an integrated executable for a heterogeneous architecture. International Business Machines Corporation, Carr, Diana R Gerhardt, April 3, 2007: US07200840 (15 worldwide citation)

In the present invention, global information is passed from a first execution environment to a second execution environment, wherein both the first and second processor units comprise separate memories. The global variable is transferred through the invocation of a memory flow controller by a stub f ...