1
Ury Priel, Jerry D Gray, Allen H Frederick: Low power write-once, read-only memory array. Monolithic Memories, Harry M Weiss, May 1, 1979: US04152627 (53 worldwide citation)

This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense amplifier of the memory array are fabricated to h ...


2
William E Moss, Shlomo Waser, Ury Priel: Bidirectional dual port serially controlled programmable read-only memory. August 30, 1983: US04402067 (30 worldwide citation)

A bidirectional serially controlled programmable read-only memory has a serial input/output (I/O) port and a parallel I/O port. By selecting the appropriate control inputs, the instant invention can receive serial address or data information and output data to either the parallel or serial I/O ports ...


3
Ronald C Laugesen, Ury Priel: Circuit for increasing the output current in MOS transistors. National Semiconductor Corporation, Gail W Woodward, Willis E Higgins, December 13, 1977: US04063117 (24 worldwide citation)

In order to increase the output current of an MOS transistor, its gate is provided with a switched capacitor drive. A tri-state inverter is used to drive the output transistor gate from an input source. A pair of delay elements are cascaded to drive one input of a NOR gate, the other input of which ...


4
Giora Yaron, Ying K Shum, Ury Priel, Jayasimha S Prasad, Mark S Ebel: Electrically programmable and erasable memory cell. National Semiconductor Corporation, Paul J Winters, Gail W Woodward, Michael J Pollock, October 16, 1984: US04477825 (22 worldwide citation)

An electrically programmable and eraseable memory cell in which charge carriers are tunnelled between a floating gate and a drain region in the substrate through a thin oxide tunnel region, the borders of said tunnel region being confined to a small area well inside the borders of both the drain reg ...


5
Ury Priel, Giora Yaron, Mark S Ebel: Memory core testing system. National Semiconductor Corporation, Michael J Pollock, Paul J Winters, Gail W Woodward, May 21, 1985: US04519076 (17 worldwide citation)

A means for testing the threshold voltage changes in a programmable and erasable floating gate memory cell by accessing directly and exclusively the cells in the core, and the amplifiers that sense the operation of the cells, so as to measure the relative currents therein as an indication of thresho ...


6
Ury Priel: Fixed voltage reference circuit. National Semiconductor Corporation, Gail W Woodward, James A Sheridan, July 7, 1981: US04277739 (17 worldwide citation)

Two output voltages are generated in response to the output of a power supply. One output is referenced to the positive supply terminal V.sub.CC and the other output is referenced to the negative supply terminal V.sub.EE.. A first .DELTA.V.sub.BE reference circuit provides for the production of the ...


7
Ury Priel, Jerry D Gray, Allen H Frederick: Fabrication of high resistivity semiconductor resistors by ion implanatation. Monolithic Memories, Harry M Weiss, April 1, 1980: US04196228 (16 worldwide citation)

This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense amplifier of the memory array are fabricated to h ...


8
Ury Priel: Sense amplifier with tri-state bus line capabilities. National Semiconductor Corporation, Lowhurst & Aine, September 14, 1976: US03980898 (16 worldwide citation)

A novel sense amplifier circuit providing conversion of MOS input signals to TTL output signals with tri-state logic output at the output data bus, the input circuit of the sense amplifier providing current sensing and programmable input thresholds for economical construction and enhanced speed of o ...


9
Ury Priel, Jerry D Gray, Allen H Frederick: High resistivity semiconductor resistor device. Monolithic Memories, Harry M Weiss, October 14, 1980: US04228451 (9 worldwide citation)

This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense amplifier of the memory array are fabricated to h ...


10
Ury Priel, Robert A Anselmo: Inverter with minimum skew. National Semiconductor Corporation, Lowhurst & Aine, June 8, 1976: US03962589 (7 worldwide citation)

A dual inverter circuit wherein the first inverter circuit includes a pair of phase splitter transistors, one serving to feed the base of the pull-up transistor in the first inverter circuit and the other serving to feed the base of the phase splitter transistor in the second inverter circuit. The c ...