1
David B Fite, John E Murray, Dwight P Manley, Michael M McKeon, Elaine H Fite, Ronald M Salett, Tryggve Fossum: Branch prediction. Digital Equipment Corporation, Arnold White & Durkee, August 25, 1992: US05142634 (188 worldwide citation)

A branch prediction is made by searching a cache memory for branch history information associated with a branch instruction. If associated information is not found in the cache, then the branch is predicted based on a predetermined branch bias for the branch instruction's opcode; otherwise, the bran ...


2
Joel S Emer, Rebecca L Stamm, Bruce E Edwards, Matthew H Reilly, Craig B Zilles, Tryggve Fossum, Christopher F Joerg, James E Hicks Jr: Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit. Compaq Information Technologies Group, Hamilton Brook Smith & Reynolds P C, December 10, 2002: US06493741 (112 worldwide citation)

Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as ...


3
Michael E Flynn, Scott Arnold, Stephen J DeLaHunt, Tryggve Fossum, Ricky C Hetherington, David J Webb: Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system. Digital Equipment Corporation, Arnold White & Durkee, June 22, 1993: US05222224 (110 worldwide citation)

A method for insuring data consistency between a plurality of individual processor cache memories and the main memory in a multi-processor computer system is provided which is capable of (1) detecting when one of a set of predefined data inconsistency states occurs as a data transaction request is b ...


4
Michael E Flynn, Tryggve Fossum: System for arbitrating communication requests using multi-pass control unit based on availability of system resources. Digital Equipment Corporation, Arnold White & Durkee, October 13, 1992: US05155854 (101 worldwide citation)

A system control unit (SCU), adapted to operating a plurality of central processor units (CPUs) in a parallel fashion in combination with at least one input/output (I/O) unit and for allowing the CPUs and I/O units to controllably access address segments of a system memory, arbitrates communication ...


5
Tryggve Fossum, Ricky C Hetherington, David B Fite Jr, Dwight P Manley, Francis X McKeen, John E Murray: Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements. Digital Equipment Corporation, Arnold White & Durkee, December 19, 1989: US04888679 (95 worldwide citation)

A main memory and cache suitable for scalar processing are used in connection with a vector processor by issuing prefetch requests in response to the recognition of a vector load instruction. A respective prefetch request is issued for each block containing an element of the vector to be loaded from ...


6
David A Webb Jr, Ricky C Hetherington, John E Murray, Tryggve Fossum, Dwight P Manley: Method and apparatus for ordering and queueing multiple memory requests. Digital Equipment Corporation, Arnold White & Durkee, June 22, 1993: US05222223 (81 worldwide citation)

In a pipelined computer system 10, memory access functions (requests) are simultaneously generated from a plurality of different locations. These multiple requests are passed through a multiplexer 50 according to a prioritization scheme based upon the operational proximity of the request to the inst ...


7
Elaine H Fite, Tryggve Fossum, William R Grundmann, Francis X McKeen, Ronald M Salett: Control of multiple functional units with parallel operation in a microcoded execution unit. Digital Equipment Corporation, Arnold White & Durkee, November 19, 1991: US05067069 (78 worldwide citation)

To increase the performance of a pipelined processor executing various classes of instructions, the classes of instructions are executed by respective functional units which are independently controlled and operated in parallel. The classes of instructions include integer instructions, floating poin ...


8
David A Webb Jr, David B Fite, Ricky C Hetherington, Francis X McKeen, Mark A Firstenberg, John E Murray, Dwight P Manley, Ronald M Salett, Tryggve Fossum: System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer. Digital Equipment Corporation, Arnold White & Durkee, January 15, 1991: US04985825 (77 worldwide citation)

A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access ...


9
Scott Arnold, James Kann, Stephen J DeLaHunt, Tryggve Fossum: Synchronizing and processing of memory access operations in multiprocessor systems using a directory of lock bits. Digital Equipment Corporation, Arnold White & Durkee, December 29, 1992: US05175837 (75 worldwide citation)

All monitoring and control of locked memory access requests in a multiprocessing computer system is handled by a system control unit (SCU) which controls the parallel operation of a plurality of central processing units (CPUs) and I/O units relative to a common main memory. Locking granularity is de ...


10
David B Fite, Tryggve Fossum, Ricky C Hetherington, John E Murray, Jr David A Webb: Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system. Digital Equipment Corporation, Arnold White & Durkee, June 23, 1992: US05125083 (73 worldwide citation)

An operand processing unit delivers a specified address and at least one read/write signal in response to an instruction being a source of destination operand, and delivers the source operand to an execution unit in response to completion of the preprocessing. The execution unit receives the source ...