1
David B Gustavson, David V James, Hans A Wiggers, Peter B Gillingham, Cormac M O&apos Connell, Bruce Millar, Jean Crepeau, Kevin J Ryan, Terry R Lee, Brent Keeth, Troy A Manning, Donald N North, Desi Rhoden, Henry Stracovsky, Yoshikazu Morooka: Memory system having synchronous-link DRAM (SLDRAM) devices and controller. Advanced Memory International, Gideon Gimlan, Fleisler Dubb Meyer & Lovejoy, August 27, 2002: US06442644 (316 worldwide citation)

A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command cl ...


2
Russel Jacob Baker, Troy A Manning: Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same. Micron Technology, Dorsey & Whitney, February 15, 2000: US06026050 (175 worldwide citation)

A system for adjusting the phase of an internal clock signal relative to an external clock signal in a packetized dynamic random access memory device. The system applies a plurality of initialization packets of the memory device that are captured in a shift register responsive to a transition of the ...


3
Troy A Manning: Memory device with staggered data paths. Micron Technology, Seed and Berry, November 3, 1998: US05831929 (163 worldwide citation)

A memory device includes input and output data sequencers that transfer data between a memory array and a data bus where transfers between the data sequencers and the data bus are controlled by a first clock signal and transfers between a memory array and the data sequencers are controlled by a seco ...


4
Brian Johnson, Brent Keeth, Troy A Manning: Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device. Micron Technology, Dickstein Shapiro Morin & Oshinsky, February 24, 2004: US06697926 (162 worldwide citation)

A method and apparatus for accurately determining the actual arrival of data at a memory device relative to the write clock to accurately align the start of data capture and the arrival of the data at the memory device is disclosed. The actual time of arrival of data at the inputs to a memory device ...


5
Paul S Zagar, Brett L Williams, Troy A Manning: Burst EDO memory device. Micron Technology, Greg A Blodgett, June 11, 1996: US05526320 (157 worldwide citation)

An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe trans ...


6
Brent Keeth, Troy A Manning, Chris G Martin, Kim M Pierce, Wallace E Fister, Kevin J Ryan, Terry R Lee, Mike Pearson, Thomas W Voshell: Method and apparatus for memory array compressed data testing. Micron Technology, Seed and Berry, August 10, 1999: US05935263 (151 worldwide citation)

A memory device includes an output data path that transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern. If the data does not match the desired pattern, the comparing circuit output ...


7
Brent Keeth, Terry R Lee, Kevin Ryan, Troy A Manning: Method and apparatus for bit-to-bit timing correction of a high speed memory bus. Micron Technology, Dorsey & Whitney, December 9, 2003: US06662304 (135 worldwide citation)

A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a plurality of digital signals applied to respective latches in the packetized memory device. A clock gen ...


8
Todd A Merritt, Troy A Manning: Distributed write data drivers for burst access memories. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, January 28, 1997: US05598376 (133 worldwide citation)

An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only r ...


9
Troy A Manning, Chris G Martin, Shubneesh Batra, Donald M Morgan: Antifuse method to repair columns in a prefetched output memory architecture. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, October 9, 2001: US06301164 (128 worldwide citation)

A memory device having a first set of programmable elements programmed to store an address of a column having a bad memory cell, and a second set of programmable elements programmed to store a segment-in-time (SIT) of the bad memory cell, the SIT of the bad memory cell indicating a relative position ...


10
Brent Keeth, Troy A Manning: Multi-bank memory input/output line selection. Micron Technology, Seed and Berry, February 9, 1999: US05870347 (115 worldwide citation)

A multi-bank memory includes memory cells arranged in individually selectable banks that share column select signals. The memory cells are addressed by a row decoder that activates word lines to couple data onto digit lines. The digit lines are coupled to input/output lines through first and second ...