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Buynoski Matthew S, Pangrle Suzette K, Okoroanyanwu Uzodinma, Tripsas Nicholas H: Self assembly of conducting polymer for formation of polymer memory cell. Advanced Micro Devices, August 10, 2006: KR1020067006389

The present invention provides a selectively conductive organic semiconductor (e.g., polymer) device that can be utilized as a memory cell. A polymer solution including a conducting polymer (22) self assembles relative to a conductive electrode (26). The process affords self-assembly such that a sho ...


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Tripsas Nicholas H, Buynoski Matthew, Pangrle Suzette K, Okoroanyanwu Uzodinma, Hui Angela T, Lyons Christopher F, Subramanian Ramkumar, Lopatin Sergey D, Ngo Minh Van, Khathuria Ashok M, Chang Mark S, Cheung Patrick K, Oglesby Jane V: Polymer memory device formed in via opening. Advanced Micro Devices, May 3, 2006: KR1020067000426

One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one ...


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Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven: Diode array architecture for addressing nanoscale resistive memory arrays. Spansion, August 24, 2007: KR1020077010971

The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction fr ...


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Ogura Jusuke, Ramsbey Mark T, Halliyal Arvind, Krivokapic Zoran, Ngo Minh Van, Tripsas Nicholas H: Monos device having buried metal silicide bit line. Spansion, August 26, 2004: KR1020047009736

A MONOS device and method for making the device has a charge trapping dielectric layer (32), such as an oxide- nitride-oxide (ONO) layer (34, 36, 38), formed on a substrate (30). A recess (44) is created through the ONO layer (32) and in the substrate (30). A metal silicide bit line (48) is formed i ...


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Tripsas Nicholas H, Okoroanyanwu Uzodinma, Pangrle Suzette K, Vanbuskirk Michael A: Stacked organic memory devices and methods of operating and fabricating. Advanced Micro Devices, June 30, 2005: KR1020057007638

The present invention provides a multi- layer organic memory device (10, 24, 28, 34, 38, 54, 58, 74, 78, 100, 700, 704) that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi- cell and multi-layer organic memory c ...


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Avanzino Steven, Sokolik Igor, Pangrle Suzette K, Tripsas Nicholas H, Shields Jeffrey A: Protection of active layers of memory cells during processing of other elements. Spansion, June 19, 2007: KR1020077010970

A method of fabricating an electronic structure by providing a conductive layer (102), providing a dielectric layer (100) over the conductive layer (102), providing first and second openings (104, 106) through the dielectric layer (100), providing first and second conductive bodies (108, 110) in the ...


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