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Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven: Diode array architecture for addressing nanoscale resistive memory arrays. Spansion, chengwei wangjin yang, October 17, 2007: CN200580039025

The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction fr ...


12
Adem Ercan, Tripsas Nicholas H: Preamorphization to minimize void information. Spansion, March 19, 2008: EP1900045-A1

Methods are described for eliminating void formation during the fabrication of and/or operation of memory cells/devices. The methods to eliminate voids may include formation of an opening on a semiconductor structure, formation of a diffusion barrier layer, deposition of a metal into the opening, pr ...


13
Tripsas Nicholas H, Okoroanyanwu Uzodinma, Pangrle Suzette K, Vanbuskirk Michael A: Stacked organic memory devices and methods of fabricating. Advanced Micro Devices, August 3, 2005: EP1559109-A1

The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes hav ...


14
Tripsas Nicholas H, Buynoski Matthew, Okoroanyanwu Uzodinma, Pangrle Suzette K: Planar polymer memory device. Advanced Micro Devices, March 1, 2006: EP1629535-A1

The present invention provides a planar polymer memory device that can operate as a non-volatile memory device. A planar polymer memory device can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and dielectric se ...


15
Ogura Jusuke, Ramsbey Mark T, Halliyal Arvind, Krivokapic Zoran, Ngo Minh Van, Tripsas Nicholas H: Monos device having buried metal silicide bit line. Fasl, September 15, 2004: EP1456885-A2

A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer and in the substrate. A metal silicide bit line is formed in the recess and bit line oxide is formed on ...


16
Tripsas Nicholas H, Buynoski Matthew, Pangrle Suzette K, Okoroanyanwu Uzodinma, Hui Angela T, Lyons Christopher F, Subramanian Ramkumar, Lopatin Sergey D, Ngo Minh Van, Khathuria Ashok M, Chang Mark S, Cheung Patrick K, Oglesby Jane V: Polymer memory device formed in via opening. Advanced Micro Devices, Tripsas Nicholas H, Buynoski Matthew, Pangrle Suzette K, Okoroanyanwu Uzodinma, Hui Angela T, Lyons Christopher F, Subramanian Ramkumar, Lopatin Sergey D, Ngo Minh Van, Khathuria Ashok M, Chang Mark S, Cheung Patrick K, Oglesby Jane V, sCOLLOPY Daniel R, February 3, 2005: WO/2005/010892

One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one ...


17
Tripsas Nicholas H, Buynoski Matthew, Okoroanyanwu Uzodinma, Pangrle Suzette K: Planar polymer memory device. Advanced Micro Devices, Tripsas Nicholas H, Buynoski Matthew, Okoroanyanwu Uzodinma, Pangrle Suzette, K, sCOLLOPY Daniel R, December 16, 2004: WO/2004/109803

The present invention provides a planar polymer memory device (100) that can operate as a non-volatile memory device. A planar polymer memory device (100) can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and d ...


18
Ogura Jusuke, Ramsbey Mark T, Halliyal Arvind, Krivokapic Zoran, Ngo Minh Van, Tripsas Nicholas H: Monos device having buried metal silicide bit line. Fasl, sCOLLOPY Daniel R, July 3, 2003: WO/2003/054964

A MONOS device and method for making the device has a charge trapping dielectric layer (32), such as an oxide-nitride-oxide (ONO) layer (34, 36, 38), formed on a substrate (30). A recess (44) is created through the ONO layer (32) and in the substrate (30). A metal silicide bit line (48) is formed in ...


19
Acker Allan R, Tripsas Nicholas H, Ogle Robert B: Silicon dioxide spacer for locos or recessed locos. Advanced Micro Devices, RODDY Richard J, May 15, 1997: WO/1997/017729

A local oxidation of silicon process directed toward reducing lateral encroachment by use of silicon dioxide spacers. A barrier oxide (120) is formed on a silicon substrate (110) and a masking layer (130) is formed over the barrier oxide layer (120). The masking layers are removed to form windows in ...


20
Tripsas Nicholas H: Dopant profile spreading for arsenic source/drain. Advanced Micro Devices, sRODDY Richard J, December 24, 1997: WO/1997/049120

An improved process for forming shallow arsenic-doped source/drain regions in MOS devices utilizes a two-step arsenic implant which lowers the surface arsenic concentration while maintaining sharp junction profile and desired junction depth. Minimizing the excess arsenic in the surface region improv ...



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