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Yasuhiro Horiba, Toshimi Kohmura: Electronic part mounting device. Ibiden, Bacon & Thomas PLLC, October 13, 1998: US05822194 (15 worldwide citation)

The present invention is to provide an electronic part mounting device including: a lamination body composed of a circuit board and a structural member; an electronic part attached in an opening formed in the lamination body; and an encapsulant layer to encapsulate the electronic part, wherein an ou ...


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Yousui Nemoto, Akiyoshi Itoh, Toshimi Kohmura, Yasuhiro Horiba: Epoxy resin-impregnated glass cloth sheet having adhesive layer. Mitsubishi Petrochemical, Oblon Spivak McClelland Maier & Neustadt, November 3, 1992: US05160783 (13 worldwide citation)

An epoxy resin-impregnated glass cloth sheet having an adhesive layer provided on at least one side of the surface thereof, characterized in that (A) said epoxy resin-impregnated glass cloth sheet is formed by impregnating glass cloth with a curable epoxy resin composition and curing it, said curabl ...


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Munehiro Toyama, Charan Gurumurthy, Toshimi Kohmura: Embedding device in substrate cavity. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 14, 2012: US08115307 (7 worldwide citation)

An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth ...


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Mikio Mori, Toshimi Kohmura: Electronic part module and process for manufacturing the same. Ibiden, Oblon Spivak McClelland Maier & Neustadt P C, October 16, 2001: US06303873 (4 worldwide citation)

An inexpensive electronic part module and a process for manufacturing the same, wherein an inexpensive thermoplastic resin is used as the substrate of the circuit board. In order to electrically connect the solder bumps of an electronic part such as an IC chip to a connection pattern, without formin ...


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Munehiro Toyama, Charan Gurumurthy, Toshimi Kohmura: Embedding device in substrate cavity. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 22, 2009: US07592202 (4 worldwide citation)

An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth ...


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Toshimi Kohmura, Yasuhiro Horiba, Hisao Kato: Primary printed wiring board. Ibiden, Bacon & Thomas PLLC, September 21, 1999: US05956237 (2 worldwide citation)

A primary printed wiring board includes: secondary printed wiring boards arranged in plural lines; main plated leads formed between the plural lines of secondary printed wiring boards; and auxiliary plated leads which connect patterns forming the secondary printed wiring boards to the main plated le ...


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Hideki Goto, Toshimi Kohmura: Delamination reduction between vias and conductive pads. Intel Corporation, Schwabe Williamson & Wyatt P C, July 1, 2008: US07394159 (2 worldwide citation)

Vias and conductive pads configured and coupled in a manner to reduce delamination are described herein. The via and the conductive pads may be located in a substrate such as a carrier substrate, a die, or a printed circuit board.


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Munehiro Toyama, Charan Gurumurthy, Toshimi Kohmura: Embedding device in substrate cavity. Blakely Sokoloff Taylor & Zafman, October 4, 2007: US20070232050-A1

An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth ...


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Hideki Goto, Toshimi Kohmura: Delamination reduction between vias and conductive pads. Intel Corporation, Schwabe Williamson & Wyatt, August 24, 2006: US20060186537-A1

Vias and conductive pads configured and coupled in a manner to reduce delamination are described herein. The via and the conductive pads may be located in a substrate such as a carrier substrate, a die, or a printed circuit board.