1
Yutaka Yoshimura, Toshiaki Tarui, Frederico Buchholz Maciel, Toru Shonai: Computer resource allocating method. Hitachi, Mattingly Stanger Malur Brundidge P C, June 13, 2006: US07062559 (97 worldwide citation)

When a load of a user is fluctuated, a data center dynamically changes resource allocation to the user according to the load and holds security for each user. A control program on a data center managing server creates a VLAN configuration table so as to allocate a user-dedicated VLAN including plura ...


2
Koichi Okazawa, Toshiaki Tarui, Yasuyuki Okada: Reliability of crossbar switches in an information processing system. Hitachi, Antonelli Terry Stout & Kraus, March 7, 2000: US06035414 (85 worldwide citation)

An information processing apparatus includes a crossbar switch having a plurality of switching circuits for data transfer; connection lines having address data transfer paths of m-bit unit connected to each of the input/output ports of the switching circuits, control signal transfer paths of m-bit u ...


3
Toshiaki Tarui, Toshio Okochi, Shinichi Kawamoto: Shared memory multiprocessor system and method with address translation between partitions and resetting of nodes included in other partitions. Hitachi, Antonelli Terry Stout & Kraus, January 21, 2003: US06510496 (81 worldwide citation)

A symmetric multiprocessor (SMP) of hierarchical connection realizing an inter-partition shared memory has at the gateway of an inter-node connection switch from each node, a translator for translating an address of an access command for an area shared between partitions, between a real address used ...


4
Tsuyoshi Tanaka, Naoki Hamanaka, Toshiaki Tarui: Virtual computer system with dynamic resource reallocation. Hitachi, Mattingly Stanger Malur & Brundidge P C, October 30, 2007: US07290259 (51 worldwide citation)

A virtual computer system including a reallocation means, in which a plurality of LPAR are operated by logically dividing physical resources composing a physical computer exclusively or in time dividing manner so as to dynamically change reallocation of physical resources among each of LPARs. Based ...


5
Toshiaki Tarui, Naonobu Sukegawa, Hiroaki Fujii, Katsuyoshi Kitai: Access control method for a shared main memory in a multiprocessor based upon a directory held at a storage location of data in the memory after reading data to a processor. Hitachi, Antonelli Terry Stout & Kraus, February 25, 1997: US05606686 (41 worldwide citation)

A main memory shared by plural processing units in a parallel computer system is composed of plural partial main memories. A directory for each data line of the main memory is generated after the data line has been cached in one of the processing units. The directory is held in one of the partial ma ...


6
Koichi Okazawa, Toshiaki Tarui, Yasuyuki Okada: Switch control method and apparatus in a system having a plurality of processors. Hitachi, Antonelli Terry Stout & Kraus, April 23, 2002: US06378021 (36 worldwide citation)

In an information processing apparatus having a crossbar switch, registers are provided for logical division of a connection of the crossbar switch into a plurality of groups, in order to allow a system to change the group division configuration while the system is in an ordinary operation. As an ap ...


7
Katsuyoshi Kitai, Yoshimasa Masuoka, Satoshi Yoshizawa, Frederico Buchholz Maciel, Toshiaki Tarui, Tatsuo Higuchi, Hideki Murahashi: Network data communication system. Hitachi, Antonelli Terry Stout & Kraus, June 11, 2002: US06404766 (29 worldwide citation)

In order to execute a flow control and a congestion control in a hop-by-hop manner in a data communication among computers connected to different networks, in a data communication between a client A


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Hiroaki Fujii, Toshiaki Tarui, Naonobu Sukegawa: Memory access mechanism for a parallel processing computer system with distributed shared memory. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, April 27, 1999: US05898883 (28 worldwide citation)

To increase the capacity of usable memory of a parallel processing computer system as a whole and effectively utilize the address space without waste, a variable-length Global/Local allocation field is provided in a fixed-length address. When the field is locally set, the address is used as an addre ...


9
Toshiaki Tarui, Koichi Okazawa, Yasuyuki Okada, Toru Shonai, Toshio Okochi, Hideya Akashi: Shared memory multiprocessor performing cache coherency. Hitachi, Beall Law Offices, July 11, 2000: US06088770 (27 worldwide citation)

A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from ...


10
Tatsuo Higuchi, Toshiaki Tarui, Katsuyoshi Kitai, Shigeo Takeuchi, Tatsuru Toba, Machiko Asaie, Yasuhiro Inagami: Exclusive control method with each node controlling issue of an exclusive use request to a shared resource, a computer system therefor and a computer system with a circuit for detecting writing of an event flag into a shared main storage. Hitachi, Hitachi ULSI Engineering, Antonelli Terry Stout & Kraus, June 30, 1998: US05774731 (26 worldwide citation)

In order to reduce load at a resource managing node for exclusive control of a shared resource, each node has a group of lock state registers each corresponding to one of the nodes. Before one node issues a lock request to a resource managing node, the node checks the register group to see if the re ...