1
Toru Watabe, Yasutomo Sakurai, Takumi Kishino, Yoshio Hirose, Koichi Odahara, Kazuhiro Nonomura, Takumi Takeno, Shinya Katoh, Takato Noda: Information processing system. Fujitsu, Staas & Halsey, November 10, 1998: US05835697 (23 worldwide citation)

A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processo ...


2
Toru Watabe, Yasutomo Sakurai, Takumi Kishino, Yoshio Hirose, Koichi Odahara, Kazuhiro Nonomura, Takumi Takeno, Shinya Katoh, Takato Noda: Information processing system. Fujitsu, Staas & Halsey, June 6, 2000: US06073249 (15 worldwide citation)

A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processo ...


3
Kenichi Kobayashi, Toru Watabe: Transaction retry in multi-processor system. Fujitsu, Staas & Halsey, February 10, 2004: US06691191 (12 worldwide citation)

An information-processing device includes a bus, a plurality of processors connected to the bus, and a bus-control unit which detects whether an excessively retried address transaction is present. Each of the processors includes an issuing unit which issues address transactions, a monitoring unit wh ...


4
Yasumasa Honjo, Toru Watabe: Multiprocessor system with system modules each having processors, and a data transfer method therefor. Fujitsu, Staas & Halsey, March 2, 2004: US06701407 (9 worldwide citation)

A multiprocessor system includes a plurality of system modules each having a plurality of processors, a transfer controller and a first crossbar, a crossbar module including a second crossbar, a control bus coupling the transfer controller of each of the system modules to the crossbar module, and a ...


5
Megumi Yokoi, Hiroshi Wachi, Kouichi Odahara, Toru Watabe, Hiroshi Murakami: Multiprocessor system and memory access method. Fujitsu, Staas & Halsey, April 12, 2005: US06880046 (3 worldwide citation)

A memory access method is employed in a multiprocessor system which includes a plurality of system modules coupled via a crossbar module, where each of the system modules includes a buffer which holds data and a plurality of processors having a cache memory which temporarily holds data. The memory a ...


6
Hiroshi Murakami, Toru Watabe: Multiprocessor system. Fujitsu, Staas & Halsey, November 21, 2002: US20020174282-A1

A multiprocessor system provided with a plurality of ports (54-1 to 54-n+m) forming processors or bus bridge units, is constructed to include a system controller (51, 51A) coupling the plurality of ports via address buses and control signal lines, a data bus controller (52) coupling the plurality of ...