1
Toru Kaga, Yoshifumi Kawamoto, Hideo Sunami: Process for manufacturing vertical dynamic random access memories. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, April 21, 1992: US05106775 (229 worldwide citation)

A semiconductor memory comprises a switching device and a charge-storage device disposed at the upper and lower sides, respectively, of each of semiconductor islands. The islands are formed on a semiconductor substrate that is completely isolated from the semiconductor substrate by an insulator. The ...


2
Dai Hisamoto, Toru Kaga, Shinichiro Kimura, Masahiro Moniwa, Haruhiko Tanaka, Atsushi Hiraiwa, Eiji Takeda: Method of manufacturing a semiconductor device having silicon islands. Hitachi, Antonelli Terry Stout & Kraus, November 14, 1995: US05466621 (94 worldwide citation)

A semiconductor device such as FET or charge coupled device, having a channel or a charge coupled portion provided in a thin semiconductor layer which is nearly perpendicular to the substrate and to which the necessary electrode such as the gate electrode and the necessary insulating layer are added ...


3
Shin ichiro Kimura, Tokuo Kure, Toru Kaga, Digh Hisamoto, Eiji Takeda: Dynamic random access memory having trench capacitors and vertical transistors. Hitachi, Antonelli Terry Stout & Kraus, January 5, 1993: US05177576 (77 worldwide citation)

A vertical semiconductor memory device is provided which capable of miniaturization. More particularly, a memory cell is provided having a trench capacitor and a vertical transistor in a dynamic random access memory suitable for high density integration. An object of this arrangement is to provide a ...


4
Dai Hisamoto, Toru Kaga, Shinichiro Kimura, Masahiro Moniwa, Haruhiko Tanaka, Atsushi Hiraiwa, Eiji Takeda: Method for manufacturing a semiconductor device and a semiconductor memory device. Hitachi, Antonelli Terry Stout & Kraus, September 13, 1994: US05346834 (66 worldwide citation)

An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate a ...


5
Noboru Moriuchi, Yoshiki Yamaguchi, Toshihiko Tanaka, Norio Hasegawa, Yoshifumi Kawamoto, Shin ichiro Kimura, Toru Kaga, Tokuo Kure: Semiconductor memory device with recessed array region. Hitachi, Antonelli Terry Stout & Kraus, March 23, 1993: US05196910 (65 worldwide citation)

A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of the semiconductor substrate having the recessed part and a projected part, and wherein a peripheral circu ...


6
Noboru Moriuchi, Yoshiki Yamaguchi, Toshihiko Tanaka, Norio Hasegawa, Yoshifumi Kawamoto, Shin ichiro Kimura, Toru Kaga, Tokuo Kure: Method of making a semiconductor memory device with recessed array region. Hitachi, Antonelli Terry & Wands, November 21, 1989: US04882289 (63 worldwide citation)

A semiconductor memory wherein a memory cell region having a plurality of memory cells and has higher altitude from the surface of semiconductor substrate is formed in the recessed part of semiconductor substrate having the recessed part and projected part and a peripheral circuit region which is co ...


7
Dai Hisamoto, Toru Kaga, Shinichiro Kimura, Masahiro Moniwa, Haruhiko Tanaka, Atsushi Hiraiwa, Eiji Takeda: Semiconductor device and semiconductor memory device. Hitachi, Antonelli Terry Stout Kraus, May 19, 1992: US05115289 (51 worldwide citation)

A semiconductor device, such as an FET or a charge coupled device, is provided having a channel or a charge coupled portion formed in a thin semiconductor layer which is substantially perpendicular to the substrate. Necessary electrodes, such as the gate electrode, and necessary insulating layers ca ...


8
Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda: Semiconductor memory device having stacked capacitor cells. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, August 18, 1992: US05140389 (51 worldwide citation)

A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portion ...


9
Toru Kaga, Shinichiro Kimura, Hideo Sunami: Semiconductor memory having trench capacitor formed with sheath electrode. Hitachi, Antonelli Terry & Wands, April 17, 1990: US04918502 (48 worldwide citation)

The present invention relates to a highly packaged semiconductor memory, and more particularly to a memory cell having a trench capacitor for use in a CMOS memory. The present invention discloses a semiconductor memory employing memory cells each constructed of a trench type charge storage capacitor ...


10
Satoshi Meguro, Kiyofumi Uchibori, Norio Suzuki, Makoto Motoyoshi, Atsuyoshi Koike, Toshiaki Yamanaka, Yoshio Sakai, Toru Kaga, Naotaka Hashimoto, Takashi Hashimoto, Shigeru Honjou, Osamu Minato: Semiconductor integrated circuit device. Hitachi, Antonelli Terry Stout & Kraus, March 16, 1993: US05194749 (44 worldwide citation)

In a memory cell of SRAM of CMOS type, load MISFET having a polycrystalline silicon film as area of source, drain and channel is stacked on drive MISFET, and gate electrodes of the drive MISFET and the load MISFET are constituted by conductive films in different layers. Area of source and drain prov ...