1
Toru Baji, Yukio Nakano, Shiro Tanabe, Tetsuya Nakagawa, Hirotsugu Kojima: Multimedia bidirectional broadcast system. Hitachi, Pennie & Edmonds, June 25, 1991: US05027400 (738 worldwide citation)

A multimedia bidirectional broadcast system including a broadcast station and subscriber terminals. The broadcast station includes a main control unit having therein a data base control table in which program and commerical down load sequences are recorded depending on a setting effected by a subscr ...


2
Toru Baji: Digital signal processor with on-chip select decoder and wait state generator. Hitachi America, Flehr Hohbach Test Albritton & Herbert, April 14, 1998: US05740404 (114 worldwide citation)

A digital signal processor (DSP) provides an improvement in the interfacing and sharing of external memory devices. Specifically, the digital signal processor is provided with a parallel interface for communicating with external memory devices, a chip select decoder located on-chip for selectably en ...


3
Toru Baji, Kouki Noguchi, Tetsuya Nakagawa, Motonobu Tonomura, Hajime Akimoto, Toshiaki Masuhara: Apparatus including a pair of neural networks having disparate functions cooperating to perform instruction recognition. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, June 20, 1995: US05426745 (68 worldwide citation)

There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for rec ...


4
Stephen G Haigh, Toru Baji: Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions. Hitachi America, Flehr Hohbach Test Albritton & Herbert, November 10, 1992: US05163139 (55 worldwide citation)

An instruction memory apparatus for a data processing unit stores a sequence of instructions. At each instruction fetch cycle, two sequentially adjacent instructions are accessed. An instruction preprocessing unit, coupled to the internal instruction memory, combines the two sequentially adjacent in ...


5
Toru Baji, Kouki Noguchi, Tetsuya Nakagawa, Motonobu Tonomura, Hajime Akimoto, Toshiaki Masuhara: Customized personal terminal device. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, November 10, 1992: US05163111 (50 worldwide citation)

There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for rec ...


6
Toru Baji, Toshihisa Tsukada, Norio Koike, Toshiyuki Akiyama, Iwao Takemoto, Shigeru Shimada, Chushirou Kusano, Shinya Ohba, Haruo Matsumaru: Solid state image pickup device. Hitachi, Antonelli Terry & Wands, September 27, 1983: US04407010 (44 worldwide citation)

A solid state image pickup device having a plurality of solid state elements in a two-dimensional array so as to form picture cells. Each solid state element includes a photoelectric converting element and a switching field effect transistor to permit scanning of the elements by scanners. To counter ...


7
Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba: Microcomputer. Hitachi, Loudermilk & Associates, February 2, 1999: US05867726 (37 worldwide citation)

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in mem ...


8
Toru Baji, Hidenori Inouchi: Systolic processor elements for a neural network. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, February 25, 1992: US05091864 (35 worldwide citation)

A neural net signal processor provided with a single layer neural net constituted of N neuron circuits which sums the results of the multiplication of each of N input signals Xj(j=1 to N) by a coefficient mij to produce a multiply-accumulate value ##EQU1## thereof, in which input signals Xj(j=1 to N ...


9
Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi: Terminal apparatus. Renesas Technology, Antonelli Terry Stout and Kraus, January 31, 2006: US06993597 (34 worldwide citation)

A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are ...


10
Atsushi Kiuchi, Toru Baji, Tetsuya Nakagawa, Kenji Kaneko: Digital signal processor and method for executing DSP and RISC class instructions defining identical data processing or data transfer operations. Hitachi America, Flehr Hohbach Test Albritton & Herbert, June 10, 1997: US05638524 (33 worldwide citation)

A digital signal processor that includes an instruction memory, a program control unit, and an instruction decoder. The instruction memory stores a sequence of instruction words including DSP instruction words and RISC instruction words. The program control unit outputs an instruction address to the ...



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