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Kozo Kimura, Tokuzo Kiyohara, Kousuke Yoshioka: Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream. Matsushita Electric Industrial, Price Gess & Ubell, August 15, 2000: US06105127 (114 worldwide citation)

A multithreaded processor for executing multiple instruction streams is provided. This multithreaded processor includes: a plurality of functional units for executing instructions; a plurality of instruction decode units, corresponding to the multiple instruction streams on a one-to-one basis, for r ...


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Kozo Kimura, Kosuki Yoshioka, Tokuzo Kiyohara: Speculative execution processor. Matsushita Electric Co, Price Gess & Ubell, April 23, 1996: US05511172 (43 worldwide citation)

The present invention discloses a speculative execution processor including a plurality of executing units for processing in parallel a plurality of instructions in an instruction sequence stored in its memory. The processor comprises an instruction type distinguishing device for distinguishing a ty ...


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Tetsuji Mochida, Tokuzo Kiyohara, Makoto Hirai, Hideshi Nishida: IMAGE DECODING APPARATUS THAT PERFORMS IMAGE DECODING SO THAT FRAME AREAS THAT OCCUPY A LARGE AREA IN A STORAGE APPARATUS CAN BE USED FOR OTHER PURPOSES, AND A RECORDING MEDIUM RECORDING AN IMAGE DECODING PROGRAM. Matsushita Electric Industrial, Price and Gess, October 8, 2002: US06462744 (31 worldwide citation)

When an OSD data storage area for storing OSD data needs to be reserved, an area of a frame storage apparatus that should store macroblocks corresponding to an invisible area on a screen is allocated as the OSD data storage area. There is no degradation in picture quality. When doing so, the data re ...


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Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara, Kozo Kimura: Media processing apparatus which operates at high efficiency. Matsushita Electric Industrial, Price and Gess, October 30, 2001: US06310921 (30 worldwide citation)

A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the inp ...


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Kozo Kimura, Tokuzo Kiyohara, Toshimichi Matsuzaki: Processing system for branch instruction. Matsushita Electric Industrial, Lowe Price LeBlanc & Becker, March 23, 1993: US05197136 (25 worldwide citation)

A storage holds instructions including a branch instruction and a corresponding branch destination instruction. The instructions are sequentially fetched from the storage to a decoder. The decoder sequentially decodes the fetched instructions and derives commands from the respective instructions. Th ...


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Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara, Kozo Kimura: Image decoder and image memory overcoming various kinds of delaying factors caused by hardware specifications specific to image memory by improving storing system and reading-out system. Matsushita Electric Industrial, Price Gess & Ubell, June 13, 2000: US06075899 (25 worldwide citation)

An image memory stores a one-screen image by dividing the one-screen image into a plurality of image blocks which are each m pixels wide by n pixels high. The image memory has an array-like storage region storing s*t first chrominance components that compose one image block and s*t second chrominanc ...


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Tetsuya Tanaka, Hazuki Okabayashi, Ryuta Nakanishi, Tokuzo Kiyohara, Takao Yamamoto, Keisuke Kaneko: N-way set associative cache memory and control method thereof. Panasonic Corporation, Greenblum & Bernstein, March 10, 2009: US07502887 (22 worldwide citation)

The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control regist ...


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Tokuzo Kiyohara, Wen mei W Hwu, William Chen: Memory conflict buffer for achieving memory disambiguation in compile-time code schedule. Matsushita Electric Industrial, The Board of Trustees of the University of Illinois, Wenderoth Lind & Ponack, December 2, 1997: US05694577 (21 worldwide citation)

An apparatus is provided, for use in a computer having a register bank and a device for operand fetch and instruction execution, for monitoring a store address to maintain coherency of preloaded data that is fetched by a load operation and should be effected by at least one subsequent store operatio ...