1
Toda Haruki: Memory device and serial-parallel data transform circuit.. Tokyo Shibaura Electric Co, May 31, 1995: EP0655741-A2 (89 worldwide citation)

In DRAM, a part of data in a row are rewritten at high speed. The memory device comprises dynamic type cell blocks (11); sense amplifiers (3) for sensing data of the cell blocks (11); latches (2) for storing data; data transfer gates for transferring data between the sense amplifiers (3) and the lat ...


2
Toda Haruki, Kuyama Hitoshi: A clock-synchronous semiconductor memory device and access method thereof.. Tokyo Shibaura Electric Co, September 22, 1993: EP0561370-A2 (62 worldwide citation)

A clock-synchronous semiconductor memory device includes many memory cells arranged in matrix, a count section (5) for counting the actual number of cycles of a continuous, externally-supplied basic clock signal, a control section (14) for inputting a row enable control signal (/RE) and the column e ...


3
Toda Haruki: Programmable resistance memory device. Kabushiki Kaisha Toshiba, Toda Haruki, ITAMI Masaru, September 30, 2004: WO/2004/084229 (46 worldwide citation)

programmable resistance memory device includes: a semiconductor substrate; at least one cell array, in which memory cells are arranged, formed above the semiconductor substrate, each the memory cell having a stack structure of a programmable resistance element and an access element, the programmable ...


4
Ohshima Shigeo, Toda Haruki: Data output circuit. Kabushiki Kaisha Toshiba, Banner Birch McKie & Beckett, April 17, 1990: US04918339 (34 worldwide citation)

When low-level data is output from a data output terminal, a plurality transistors, whose source-drain paths are inserted in parallel between the data output terminal and a power source terminal, begin to conduct at successively different time-points. Thus, the potential fluctuations produced in the ...


5
Toda Haruki: Phase change memory device. Kabushiki Kaisha Toshiba, Toda Haruki, ITAMI Masaru, September 30, 2004: WO/2004/084228 (28 worldwide citation)

A phase change memory device includes a substrate, a plurality of cell arrays stacked above the substrate and each including a matrix layout of a plurality of memory cells, each the memory cell storing therein as data a resistance value determinable by a phase change, a write circuit configured to w ...


6
Toda Haruki C O Patent Divisio, Sahara Hiroshi C O Patent Divi, Ohshima Shigeo C O Patent Divi: Semiconductor memory device.. Tokyo Shibaura Electric Co, October 5, 1988: EP0284985-A2 (26 worldwide citation)

A semiconductor memory device determines a level of a select control signal according to a level of drive signals for two systems as generated in the preceding access cycle, and a level of the least significant bit of an address to fetch data in a desired serial access cycle. According to this selec ...


7
Toda Haruki: Phase change memory device. Kabushiki Kaisha Toshiba, Toda Haruki, ITAMI Masaru, October 21, 2004: WO/2004/090984 (24 worldwide citation)

A phase change memory device has a semiconductor substrate; a plurality of cell arrays stacked above the semiconductor substrate, each cell array having memory cells arranged in a matrix manner for storing resistance values as data that are determined by phase change of the memory cells, bit lines e ...


8
Toda Haruki Intellectual Prope: Semiconductor memory device with memory cells including ferroelectric capacitors.. Tokyo Shibaura Electric Co, April 25, 1990: EP0364813-A2 (19 worldwide citation)

A semiconductor memory device includes bit line pairs including first and second bit lines (BL, BL) to be set at a first logic level or a second logic level, and a first memory cell (MC1) coupled with the first bit line (BL) of the bit line pairs. The first memory cell contains a first ferroelectric ...


9
Toda Haruki, Ohshima Shigeo, Ikawa Tatsuo: Semiconductor memory device.. Tokyo Shibaura Electric Co, March 21, 1990: EP0359203-A2 (16 worldwide citation)

Memory cells (12,22...N2) disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is s ...


10
Toda Haruki: Nonvolatile semiconductor storage device and electronic device using the same. Toshiba, November 11, 2004: JP2004-319007 (15 worldwide citation)

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which can be read at high-speed and has a large storage capacity, and an electronic device using the same.SOLUTION: This nonvolatile semiconductor storage device is provided with: a memory cell array in which a plurality of ...