1
Timothy M Lacey, David L Johnson: Programmable logic device. Cypress Semiconductor, Christopher P Maiorana PC, March 8, 2005: US06864710 (96 worldwide citation)

A programmable logic device comprising one or more horizontal routing channels, one or more vertical routing channels, and a logic element. Each logic element may be configured to connect between one of the horizontal routing channels and one of the vertical routing channels. The logic element may c ...


2
Timothy M Lacey, Christopher S Norris: Memory with minimized redundancy access delay. Cypress Semiconductor Corporation, Blakely Sokoloff Taylor & Zafman, January 10, 1995: US05381370 (57 worldwide citation)

A memory is described that includes a main memory array having a plurality of main memory locations and a redundant memory array having a plurality of redundant memory locations. A main decoding circuit is coupled to the main memory array for decoding an address received from an external circuit to ...


3
Timothy M Lacey, David L Johnson: Configurable memory for programmable logic circuits. Cypress Semiconductor, Christopher P Malorana P C, Robert M Miller, May 14, 2002: US06388464 (54 worldwide citation)

An apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate th ...


4
Timothy M Lacey, David L Johnson: Configurable memory for programmable logic circuits. Cypress Semiconductor, Christopher P Maiorana P C, Robert M Miller, January 28, 2003: US06512395 (50 worldwide citation)

An apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate th ...


5
Timothy M Lacey, Jeffrey Mark Marshall, David L Johnson: Multiple voltage supply programmable logic device. Cypress Semiconductor, Christopher P Maiorana P C, May 7, 2002: US06384628 (36 worldwide citation)

A programmable logic device comprising a core circuit, a first circuit, a second circuit, and a third circuit. The core circuit may be configured to (i) operate at a first supply voltage, (ii) receive one or more internal input signals, and (iii) generate one or more internal output signals. The fir ...


6
Christopher S Norris, Timothy M Lacey: Memory architecture for burst mode access. Cypress Semiconductor, Blakely Sokoloff Taylor & Zafman, September 26, 1995: US05453957 (29 worldwide citation)

The burst mode memory architecture using interleaved memory arrays provides even and odd EPROM arrays with data having even addresses stored in the even array and data having odd addresses stored in the odd array. A control circuit receives an initial address from a memory system controller and then ...


7
James MacArthur, Timothy M Lacey: Techniques and circuits for high yield improvements in programmable devices using redundant routing resources. QuickLogic Corporation, Skjerven Morrill MacPherson Franklin & Friel, July 20, 1999: US05925920 (28 worldwide citation)

The present invention provides a method and apparatus for high yield improvements in programmable logic devices using redundancy. The present invention concerns a programmable logic device comprising a plurality of routings lines coupled to a plurality of logic blocks when programmed. During program ...


8
Timothy M Lacey: Apparatus and method for improving common mode noise rejection in pseudo-differential sense amplifiers. Cypress Semiconductor, Blakely Sokoloff Taylor & Zafman, June 10, 1997: US05638322 (26 worldwide citation)

A pseudo-differential sense amplifier with improved common mode noise rejection is disclosed. The sense amplifier is connected to a memory cell via an array path and generates an output signal indicative of the state of the memory cell. The sense amplifier includes an array load device connected via ...


9
Timothy M Lacey: Decoding scheme for reliable multi bit hot electron programming. Cypress Semiconductor, Blakely Sokoloff Taylor & Zafman, November 21, 1995: US05469384 (23 worldwide citation)

A nonvolatile memory circuit having a decoding scheme for reliable multiple bit hot electron programming. The nonvolatile memory circuit has a memory array in which data received at each data input can be programmed into multiple memory bits simultaneously. The address of each memory bit selected fo ...


10
James MacArthur, Timothy M Lacey: Techniques and circuits for high yield improvements in programmable devices using redundant logic. QuickLogic Corporation, Skjerven Morrill MacPherson Franklin and Friel, November 14, 2000: US06148390 (21 worldwide citation)

A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a plurality of routing resources and a programming circuit. Good logic blocks are enabled and fully operationa ...