1
Timothy J Slegel, Lisa C Heller, Erwin F Pfeffer, Kenneth E Plambeck: Method, system and program product for invalidating a range of selected storage translation table entries. International Business Machines Corporation, John E Campbell, March 27, 2007: US07197601 (50 worldwide citation)

Selected units of storage, such as segments of storage or regions of storage, may be invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associat ...


2
Douglas G Balazich, Michael Billeci, Anthony Saporito, Timothy J Slegel: Error accumulation register, error accumulation method, and error accumulation system. International Business Machines Corporation, John E Campbell, Ido Tuchman, September 28, 2010: US07805634 (35 worldwide citation)

In operating a dual core processor, a register file collects a history of the error state information for each core. The core error state data can be analyzed to understand the recovery sequence of events. The recorded error sequence over time presents a detailed history of the recovery sequence whi ...


3
Dan F Greiner, Timothy J Slegel, Joachim von Buttlar: Rotate then operate on selected bits facility and instructions therefore. International Business Machines Corporation, John E Campbell, February 22, 2011: US07895419 (30 worldwide citation)

A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the s ...


4
Dan F Greiner, Timothy J Slegel: Extract cache attribute facility and instruction therefore. International Business Machines Corporation, John E Campbell, March 6, 2012: US08131934 (29 worldwide citation)

A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.


5
Timothy J Slegel, Lisa C Heller, Erwin F Pfeffer, Kenneth E Plambeck: Invalidating storage, clearing buffer entries, and an instruction therefor. International Business Machines Corporation, John E Campbell, October 16, 2007: US07284100 (28 worldwide citation)

Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated ...


6
Patrick M West Jr, Vimal M Kapadia, Christopher A Krygowski, Timothy J Slegel: Method, system and computer program product for failure analysis implementing automated comparison of multiple reference models. International Business Machines Corporation, Cantor Colburn, John Campbell, March 15, 2011: US07908518 (28 worldwide citation)

System, method and computer program products for failure analysis implementing automated comparison of multiple reference models. An exemplary embodiment includes a method for failure analysis for an instruction set implementation in a computer system, the method including running a test-case in a f ...


7
Dan F Greiner, Lisa C Heller, Damian L Osisek, Erwin Pfeffer, Timothy J Slegel, Charles F Webb: Dynamic address translation with translation table entry format control for indentifying format of the translation table entry. International Business Machines Corporation, John E Campbell, January 24, 2012: US08103851 (27 worldwide citation)

What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry ...


8
Brian K Cesare, Timothy J Slegel, Darell S Whitaker: Method and apparatus for error recovery in arrays. International Business Machines Corporation, Michael J Scheer, Robert L Troike, January 5, 1993: US05177744 (25 worldwide citation)

Method and apparatus for error recovery in primary storage is provided by backup storage that stores a complete copy of primary storage. When a parity error is detected, the backup storage is used to replace data in the primary storage or the parity of primary storage. This apparatus is controlled b ...


9
Timothy J Slegel, Jane H Bartik, Lisa C Heller, Erwin F Pfeffer, Ute Gaertner: Blocking processing restrictions based on addresses. International Business Machines Corporation, Lynn L Augspurger Esq, Blanche E Schiller Esq, Heslin Rothenberg Farley & Mesiti P C, February 7, 2006: US06996698 (21 worldwide citation)

Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that fetching of storage keys is prohibited, in response to a buffer miss. When a processing unit of ...


10
Christian Jacobi, Marcel Mitran, Timothy J Slegel, Charles F Webb: Load pair disjoint facility and instruction therefore. International Business Machines Corporation, William A Kinnaman Jr, September 30, 2014: US08850166 (16 worldwide citation)

A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores ...