1
Zahid S Hussain, Timothy J Millet: Method and apparatus for rasterizing in a hierarchical tile order. Microsoft Corporation, Woodcock Washburn, May 9, 2006: US07042460 (55 worldwide citation)

A method and apparatus for efficiently rasterizing graphics is provided. The method is intended to be used in combination with a frame buffer that provides fast tile-based addressing. Within this environment, frame buffer memory locations are organized into a tile hierarchy. For this hierarchy, smal ...


2
Zahid S Hussain, Timothy J Millet: Packetized command interface to graphics processor. Silicon Grahphics, Graham & James, June 13, 2000: US06075546 (50 worldwide citation)

A method and apparatus for transferring commands to a graphics processor is provided. The method and apparatus are intended for use in a host computer system having a memory that is addressable by a host processor and a graphics processor. One or more queues of packet descriptors are maintained in t ...


3
Guy Cote, Jeffrey E Frederiksen, Joseph P Bratt, Shun Wai Go, Timothy J Millet: Dual image sensor image processing system and method. Apple, Fletcher Yoder PC, July 23, 2013: US08493482 (33 worldwide citation)

Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processi ...


4
Zahid S Hussain, Timothy J Millet: Method and apparatus for rasterizing in a hierarchical tile order. Microsoft Corporation, Woodcock Washburn, August 26, 2003: US06611272 (32 worldwide citation)

A method and apparatus for efficiently rasterizing graphics is provided. The method is intended to be used in combination with a frame buffer that provides fast tile-based addressing. Within this environment, frame buffer memory locations are organized into a tile hierarchy. For this hierarchy, smal ...


5
Timothy J Millet, Muditha Kanchana, Shailendra S Desai: Coherence switch for I/O traffic. Apple, Rory D Rankin, Meyertons Hood Kivlin Kowert & Goetzel P C, November 3, 2015: US09176913 (29 worldwide citation)

A system, apparatus, and method for routing traffic in a SoC from I/O devices to memory. A coherence switch routes coherent traffic through a coherency port on a processor complex to a real-time port of a memory controller. The coherence switch routes non-coherent traffic to a non-real time port of ...


6
James Wang, Zongjian Chen, James B Keller, Timothy J Millet: Combined transparent/non-transparent cache. Apple, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P C, March 10, 2015: US08977818 (18 worldwide citation)

In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non ...


7
James Wang, Zongjian Chen, James B Keller, Timothy J Millet: Block-based non-transparent cache. Apple, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P C, July 10, 2012: US08219758 (16 worldwide citation)

In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent m ...


8
James Wang, Zongjian Chen, James B Keller, Timothy J Millet: Cache implementing multiple replacement policies. Apple, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P C, March 5, 2013: US08392658 (11 worldwide citation)

In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding ...


9
David G Conroy, Timothy J Millet, Joseph P Bratt: Hardware-based power management of functional blocks. Apple, Fletcher Yoder PC, July 19, 2011: US07984317 (10 worldwide citation)

A system and method is disclosed for efficiently managing power distribution among the various functional blocks used within portable electronic devices. The method includes allowing each functional block to be independently controlled, containing its own low-level software and power controls for se ...


10
Zahid S Hussain, Timothy J Millet: Packetized command interface to a graphics processor. Silicon Graphics Incorporated, Squire Sanders & Dempsey L, December 18, 2001: US06331857 (10 worldwide citation)

A method and apparatus for transferring commands to a graphics processor is provided. The method and apparatus are intended for use in a host computer system having a memory that is addressable by a host processor and a graphics processor. One or more queues of packet descriptors are maintained in t ...