1
Gilbert M Wolrich, Timothy C Fischer, John A Kowaleski Jr: Rounding adder for floating point processor. Digital Equipment Corporation, Diane C Drozenski, Ronald C Hudgens, Arthur W Fisher, December 2, 1997: US05694350 (23 worldwide citation)

A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding ...


2
Gilbert M Wolrich, Timothy C Fischer, John A Kowaleski Jr: Floating point unit data path alignment. Digital Equipment Corporation, Denis G Maloney, Arthur W Fisher, May 6, 1997: US05627773 (23 worldwide citation)

A pipelined floating point processor including an add pipe for performing floating point additions described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding ad ...


3
Timothy C Fischer, Samuel Naffziger, Benjamin J Patella: Count calibration for synchronous data transfer between clock domains. Hewlett Packard Development Company, July 15, 2008: US07401245 (20 worldwide citation)

Systems and methods for implementing count calibration for synchronous data transfer between clock domains are disclosed. An exemplary system may include a count calibration circuit for determining latency between an early clock domain and a late clock domain. The system may also include a data path ...


4
Gilbert M Wolrich, Timothy C Fischer, John J Ellis, Patricia L Kroesen: Fast determination of floating point sticky bit from input operands. Diane C Drozenski, Ronald C Hudgens, Arthur W Fisher, April 21, 1998: US05742537 (5 worldwide citation)

A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding ...


5
James A Farrell, Timothy C Fischer, Daniel L Leibholz, Bruce A Gieseke: Method for compacting an instruction queue. Hewlett Packard Development Company, March 9, 2004: US06704856 (5 worldwide citation)

A method of compacting an instruction queue in an out of order processor includes determining the number of invalid instructions below and including each row in the queue, by counting invalid bits or validity indicators associated with rows below and up to the current row. For each row, multiplexor ...


6
Daming Jin, Timothy C Fischer: System and method for checking bits in a buffer with multiple entries. Hewlett Packard Development Company, December 2, 2003: US06658505 (5 worldwide citation)

A computer hardware system is disclosed for determining during a single clock cycle whether a data buffer having a plurality of entries can accept additional data. The system has multiple stages, having one or more adders/encoders that process the data buffer entries' valid bits in parallel. Gr ...


7
Gilbert M Wolrich, Timothy C Fischer, John J Ellis: Normalization shift prediction independent of operand substraction. Digital Equipment Corporation, February 2, 1999: US05867407 (4 worldwide citation)

A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding ...


8
Timothy C Fischer, Samuel Naffziger: System and method for synchronizing multiple variable-frequency clock generators. Hewlett Packard Development Company, July 11, 2006: US07076679 (3 worldwide citation)

In one embodiment, a central processing unit (CPU) includes multiple clock zones. Each clock zone includes at least one sensor that generates a signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to the clock zone, a first con ...


9
Timothy C Fischer, Samuel Naffziger, Benjamin J Patella: Adaptable data path for synchronous data transfer between clock domains. Hewlett Packard Development Company, January 13, 2009: US07477712 (2 worldwide citation)

Systems and methods for implanting synchronous data transfer between clock domains are disclosed. An exemplary system may comprise an adaptable data path having an input for receiving a signal from a first clock domain and an output in a second clock domain. A controller is operatively associated wi ...


10
Gilbert M Wolrich, Timothy C Fischer, John J Ellis: Normalization shift prediction independent of operand subtraction. Digital Equipment Corporation, Hamilton Brook Smith & Reynolds P C, August 8, 2000: US06101516 (2 worldwide citation)

A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding ...