1
Tiao Yuan Huang: Double implanted LDD transistor self-aligned with gate. Xerox Corporation, Serge Abend, March 6, 1990: US04907048 (111 worldwide citation)

An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment members and a heavily doped juncti ...


2
Tiao Yuan Huang: Method for fabricating double implanted LDD transistor self-aligned with gate. Xerox Corporation, Serge Abend, October 16, 1990: US04963504 (81 worldwide citation)

An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment member and a heavily doped junctio ...


3
Horng Chih Lin, Tiao Yuan Huang: Structure and method for manufacturing improved FETs having T-shaped gates. National Science Council, Townsend and Townsend and Crew, July 21, 1998: US05783479 (61 worldwide citation)

A structure and method for manufacturing improved FETs having T-shaped gates can reduce the parasitic resistance of the gate and source/drain of an FET. In the improved FETs having T-shaped gates formed according to the invention, since a buffer layer under spacers comprises a gate oxide layer and a ...


4
Anne Chiang, I Wei Wu, Tiao Yuan Huang: Formation of large grain polycrystalline films. Xerox Corporation, Serge Abend, February 27, 1990: US04904611 (45 worldwide citation)

A method of forming large grain polycrystalline films by deep ion implantation into a composite structure, comprising a layer of amorphous semiconductor material upon an insulating substrate. Implantation is of a given ion species at an implant energy and dosage sufficient to distrupt the interface ...


5
Tiao Yuan Huang, Anne Chiang, I Wei Wu: Simultaneously deposited thin film CMOS TFTs and their method of fabrication. Xerox Corporation, Serge Abend, August 21, 1990: US04951113 (36 worldwide citation)

A thin film SOI CMOS device wheren the suitably doped deposited layers of an n-channel transistor and a p-channel transistor are simultaneously deposited. The source and drain elements of one transistor and the gate element of the other transistor are formed in a lower, highly doped, semiconductor l ...


6
Tiao Yuan Huang, Anne Chiang, I Wei Wu: Method of fabrication a thin film SOI CMOS device. Xerox Corporation, Serge Abend, January 29, 1991: US04988638 (28 worldwide citation)

A thin film SOI CMOS device wherein the suitably doped deposited layers of an n-channel transistor and a p-channel transistor are simultaneously deposited. The source and drain elements of one transistor and the gate element of the other transistor are formed in a lower, highly doped, semiconductor ...


7
Tiao Yuan Huang: Intra-gate offset high voltage thin film transistor with misalignment immunity and method of its fabrication. Xerox Corporation, Serge Abend, July 31, 1990: US04945067 (23 worldwide citation)

A high voltage thin film transistor comprising a substrate upon which is supported a non-single crystal semiconductor active layer, spaced from a pair of conductive gate electrodes by a gate dielectric layer, wherein one of the gate electrodes in the device control electrode and the other is a dummy ...


8
Tiao Yuan Huang: CMOS output buffer with enhanced ESD resistance. VLSI Technology, Clifton L Anderson, May 14, 1996: US05517049 (23 worldwide citation)

The present invention provides a CMOS integrated circuit in which core transistors are provided with punch-through pockets, while the input/output transistors are not provided with punch-through pockets. Punch-through protection for the input/output transistors by virtue of their larger dimensions. ...


9
Tiao Yuan Huang: Differential treatment to selectively avoid silicide formation on ESD I/O transistors in a salicide process. VLSI Technology, Douglas L Weller, May 9, 1995: US05413969 (21 worldwide citation)

Selective salicidation of source/drain regions of a transistor is accomplished by differentially treating a first subset of the source/drain regions to hinder formation of metal-silicide over the first subset of the source/drain regions. A metal layer is formed over the first subset of the source/dr ...


10
Tiao Yuan Huang: Forming a MOS transistor with a recessed channel. VLSI Technology, Clifton L Anderson, September 29, 1998: US05814544 (20 worldwide citation)

A MOS transistor is fabricated by forming an inverse gate mask consisting of a lower silicon dioxide layer and an upper silicon nitride layer. The exposed channel region is thermally oxidized. The mask is removed to permit a source/drain implant. The oxide growth is removed so that the channel regio ...