1
David Chiang, Napoleon W Lee, Thomas Y Ho, David A Harrison, Nicholas Kucharewski Jr, Jeffrey H Seltzer: Macrocell with product-term cascade and improved flip flop utilization. Xilinx, Edel M Young, Norman R Klivans, October 18, 1994: US05357153 (166 worldwide citation)

A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product t ...


2
Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck, Shun Wai Go, Lindy Fung, Tuan D Nguyen, Joseph P Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan Wei Tsay: Deferred shading graphics pipeline processor having advanced features. Apple Computer, R Michael Ananian, Dorsey & Whitney, April 6, 2004: US06717576 (151 worldwide citation)

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphic ...


3
Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck: Graphics processor with deferred shading. Apple Computer, R Michael Ananian, Dorsey & Whitney, July 22, 2003: US06597363 (133 worldwide citation)

Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage ...


4
Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck: Deferred shading graphics pipeline processor. Apple Computer, Flehr Hohbach Test Albritton & Herbert, May 8, 2001: US06229553 (86 worldwide citation)

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is Deferred Shading Graphics Processor (DSGP) comprising a ...


5
Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck, Shun Wai Go, Lindy Fung, Tuan D Nguyen, Joseph P Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan Wei Tsay: Deferred shading graphics pipeline processor having advanced features. Apple Computer, Dorsey & Whitney, January 23, 2007: US07167181 (68 worldwide citation)

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphic ...


6
Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck: Deferred shading graphics pipeline processor. Apple Computer, Flehr Hohbach Test Albritton & Herbert, July 31, 2001: US06268875 (60 worldwide citation)

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is a Deferred Shading Graphics Processor (DSGP) comprising ...


7
David Chiang, Thomas Y Ho, Wei Yi Ku, George H Simmons, Robert W Barker: Programmable logic device having security elements located amongst configuration bit location to prevent unauthorized reading. Xilinx, Edel M Young, Norman R Klivans, September 20, 1994: US05349249 (31 worldwide citation)

More than one security bit is used in a block of a PLD chip. The internal configuration and other information is left unprotected when all the security bits are in the erased state, and is protected by programming one or all the security bits. The security bits are located physically in proximity to ...


8
David Chiang, Thomas Y Ho, Jeffrey H Seltzer, Jeffrey Goldberg: Input circuit block and method for PLDs with register clock enable selection. Xilinx, Edel M Young, Norman R Klivans, April 12, 1994: US05302866 (25 worldwide citation)

An input block for PLDs programmable logic devices) has a flip-flop including a master latch and a slave latch, a pad for inputting data, configuration bits, and a global clock input signal for clocking the input data to the flip-flop means. The flip-flop is controlled by the configuration bits so a ...


9
Jack Benkual, Thomas Y Ho, Jerome F Duluk Jr: System, apparatus, method, and computer program for execution-order preserving uncached write combine operation. Apple Computer, R Michael Ananian, Dorsey & Whitney, December 30, 2003: US06671747 (20 worldwide citation)

A mechanism that allows an application program running on a processor, to send data to a device using a medium that temporarily stores data and changes the order of the data dispatch on the way to the device. An inventive Random-In-First-Out (RIFO) buffer or memory device that restores the original ...


10
David Chiang, Napoleon W Lee, Thomas Y Ho, Nicholas Kucharewski Jr: Multiplexed by-passable memory devices with increased speed and improved flip-flop utilization. Xilinx, Norman R Klivans, Edel M Young, October 29, 1996: US05570051 (13 worldwide citation)

A memory device, with increased storage speed and enhanced memory utilization, can be implemented by using multiplex clocking and efficient device design and enhanced flip-flop utilization. Transit time through the circuit, and hence circuit speed, can be controlled through multiplexed clock signals ...