1
Brian S Hausauer, Christopher J Pettey, Thomas R Seeman: Delayed transaction protocol for computer system bus. Compaq Computer Corporation, Sharp Comfort & Merrett P C, February 9, 1999: US05870567 (56 worldwide citation)

A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embo ...


2
Bassam Elkhoury, Christopher J Pettey, Dwight Riley, Thomas R Seeman, Brian S Hausauer: Bus-to-bus bridge in computer system, with fast burst memory range. Compaq Computer Corporation, November 10, 1998: US05835741 (39 worldwide citation)

A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embo ...


3
Peter Michels, Christopher J Pettey, Thomas R Seeman, Brian S Hausauer: Lock protocol for PCI bus using an additional "superlock" signal on the system bus. Compaq Computer, Williams Morgan & Amerson P C, August 1, 2000: US06098134 (26 worldwide citation)

A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embo ...


4
Thomas R Seeman: Computer system using posted memory write buffers in a bridge to implement system management mode. Compaq Computer Corporation, March 9, 1999: US05881253 (19 worldwide citation)

A computer system using posted memory write buffers in a bridge can implement the system management mode without faulty operation. The system management interrupt acknowledge signal is posted in bridge buffers so that any previously posted memory write commands currently held in a posted memory writ ...


5
Jon M Huppenthal, Thomas R Seeman, Lee A Burton: Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format. SRC Computers, William J Kubida, Michael C Martensen, Hogan & Hartson, May 13, 2008: US07373440 (17 worldwide citation)

A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that oth ...


6
Jon M Huppenthal, Thomas R Seeman, Lee A Burton: Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port. SRC Computers, William J Kubida, Michael C Martensen, Hogan & Hartson, February 21, 2006: US07003593 (16 worldwide citation)

A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the m ...


7
Sompong Paul Olarig, Thomas R Seeman, Kenneth Jansen, Dwight D Riley: Method and apparatus for multiplexing and demultiplexing addresses of registered peripheral interconnect apparatus. Compaq Information Technologies Group, Conley Rose & Tayon P C, September 10, 2002: US06449677 (14 worldwide citation)

A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued o ...


8
Thomas R Seeman: Computer system with bridges having posted memory write buffers. Compaq Computer Corporation, Sharp Comfort & Merrett P C, July 4, 2000: US06085274 (10 worldwide citation)

A computer system using posted memory write buffers in a bridge can implement the system management mode without faulty operation. The system management interrupt acknowledge signal is posted in bridge buffers so that any previously posted memory write commands currently held in a posted memory writ ...


9
Bassam Elkhoury, Christopher J Pettey, Dwight Riley, Thomas R Seeman, Brian S Hausauer: Bus-to-bus bridge in computer system, with fast burst memory range. Compaq Computer Corporation, Sharp Comfort & Merrett P C, November 14, 2000: US06148359 (10 worldwide citation)

A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embo ...


10
Jon M Huppenthal, Thomas R Seeman, Lee A Burton: Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers. SRC Computers, William J Kubida, Carol W Burton, Hogan & Hartson, March 27, 2007: US07197575 (8 worldwide citation)

A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particul ...