1
Bardwell C Salmon, John D Borgman, Thomas O Holtey: Computer-assisted system for interactively brokering goods or services between buyers and sellers. Eagleview, Fish & Richardson P C, January 7, 1997: US05592375 (599 worldwide citation)

A computer-implemented system for brokering transactions between sellers and a buyer of goods or services, including a database, a seller interface, and a buyer's interface. The database contains information, including multimedia information, descriptive of respective ones of the goods or services. ...


2
Thomas O Holtey, Peter J Wilson: Secure memory card. Bull HN Information Systems, Faith F Driscoll, John S Solakian, March 8, 1994: US05293424 (227 worldwide citation)

A secure memory card includes a microprocessor on a single semiconductor chip and one or more non-volatile addressable memory chips. The microprocessor chip and non-volatile memory chips connect in common to an internal card bus for transmitting address, data and control information to such non-vola ...


3
Thomas O Holtey: Secure memory card with programmed controlled security access control. Bull NH Information Systems, Faith F Driscoll, John S Solakian, August 15, 1995: US05442704 (130 worldwide citation)

A secure memory card includes a microprocessor on a single semiconductor chip which interconnects through an internal bus to a number of non-volatile addressable memory chips. The microprocessor includes an addressable non-volatile memory for storing information including a number of key values and ...


4
Thomas O Holtey: Secure application card for sharing application data and procedures among a plurality of microprocessors. Bull HN Information Systems, Faith F Driscoll, John S Solakian, February 13, 1996: US05491827 (98 worldwide citation)

An application memory card system includes a secure memory card which can be operatively connected to communicate with a host mainframe microprocessor or hand held device host microprocessor via a standard interface. The secure memory card contains an application processor and an access control micr ...


5
Thomas F Joyce, Thomas O Holtey: Private cache-to-CPU interface in a bus oriented data processing system. Honeywell Information Systems, Nicholas Prasinos, Ronald T Reiling, July 10, 1979: US04161024 (53 worldwide citation)

A data processing system having a system bus; a plurality of system units including a main memory, a cache memory, a central processing unit (CPU) and a communications controller all connected in parallel to the system bus. The controller operates to supervise interconnection between the units via t ...


6
Thomas O Holtey: I/O Request interrupt mechanism. Honeywell Information Systems, Nicholas Prasinos, September 22, 1981: US04291371 (53 worldwide citation)

Apparatus for intercepting a channel program that is operative with a particular input/output device when an input/output device of higher priority requests service. The channel program is intercepted at a time when the processor is required to process a minimum of information. This enables the proc ...


7
Thomas F Joyce, Thomas O Holtey, William Panepinto Jr: Continuous updating of cache store. Honeywell Information Systems, Nicholas Prasinos, Ronald T Reiling, September 11, 1979: US04167782 (40 worldwide citation)

A data processing system includes a plurality of system units all connected in common to a system bus. Included are a main memory system and a high speed buffer or cache store. System units communicate with each other over the system bus. Apparatus in the cache store monitors each communication betw ...


8
Thomas S Hirsch, James W Stonier, Thomas O Holtey: Microcomputer system with independent operating systems. Honeywell Bull, Nicholas Prasinos, John S Solakian, January 26, 1988: US04722048 (37 worldwide citation)

A computer system is described wherein two independent processors communicate via a bus system and operate substantially concurrently, each computer having its own operating system software and share a common memory. The architecture of the computer system is such that one of the processors is alloc ...


9
Victor Firoiu, Eric Haversat, Thomas O Holtey: Feedback output queuing system, apparatus, and method. Nortel Networks, McGuinness & Manaras, January 2, 2007: US07158480 (34 worldwide citation)

A feedback output queuing system, apparatus, and method controls the rate at which packets are forwarded from the ingress ports to a particular output queue over the switching/routing fabric based upon the level of congestion at the output queue. The output queue is monitored and the level of conges ...


10
Thomas F Joyce, Thomas O Holtey: Multi-configurable cache store system. Honeywell Information Systems, Nicholas Prasinos, Ronald T Reiling, March 25, 1980: US04195342 (34 worldwide citation)

In a data processing system which includes a plurality of system units such as a central processing unit (CPU), main memory, and cache memory all connected in common to a system bus and communicating with each other via the system bus, and also having a private CPU-cache memory interface for permitt ...



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