1
Thomas F Heil, Martin H Francis, Rodney A DeKoning, Bret S Weber: System and method for peer-to-peer accelerated I/O shipping between host bus adapters in clustered computer network. LSI Logic Corporation, January 9, 2001: US06173374 (239 worldwide citation)

The present invention retrieves data across independent computer nodes of a server cluster by providing for I/O shipping of block level requests to peer intelligent host-bus adapters (hereinafter referred to as HBA). This peer-to-peer distribution of block I/O requests is transparent to the host. Th ...


2
Thomas F Heil, Craig A Walrath, Jeff A Hawkey, Jim D Pike: Multi-port processor with peripheral component interconnect port and rambus port. NCR Corporation, George H Gates, Paul J Maginot, February 21, 1995: US05392407 (89 worldwide citation)

A dual-port processor architecture wherein a first port interfaces to a PCI bus and a second port interfaces to a RAMBUS channel.


3
Thomas F Heil: Network interface for multiplexing and demultiplexing isochronous and bursty data streams in ATM networks. AT&T Global Information Solutions Company, September 12, 1995: US05450411 (75 worldwide citation)

An asynchronous transfer mode network interface is provided to multiplex isochronous and bursty data traffic over a single logical connection. Isochronous data is received by the network interface and stored in a buffer for subsequent multiplexing with bursty data received and stored in a buffer and ...


4
Thomas F Heil, Craig A Walrath, Jimmy D Pike, Edward A McDonald, Arthur F Cochcroft Jr, P Chris Raeuber, Daniel C Robbins, Gene F Young: Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces. NCR Corporation, Richard C Stevens, October 25, 1994: US05359715 (55 worldwide citation)

Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O ...


5
Thomas F Heil: Bus system with cache snooping signals having a turnaround time between agents driving the bus for keeping the bus from floating for an extended period. NCR Corporation, George Gates, June 18, 1996: US05528764 (47 worldwide citation)

A Peripheral Component Interconnect (PCI) bus for component level interconnection of processors, peripherals and memories. The PCI bus is a physical interconnect apparatus intended for use between highly integrated peripheral controller components and processor/memory systems. The PCI bus is intende ...


6
Larry C James, Carl W Kagy, Jeffrey F Gates, Jeffrey A Hawkey, Thomas F Heil, David L Simpson: Computer system configuration via test bus. NCR Corporation, Jack R Penrod, August 30, 1994: US05343478 (43 worldwide citation)

System configuration, monitoring and control functions are performed in a computer system by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct one or more modules of the system. The conventional serial ...


7
Stephen A Fischer, Erez Carmel, Thomas F Heil: Efficient memory controller with an independent clock. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 24, 1993: US05239639 (42 worldwide citation)

A means and a method of interfacing a memory controller with a high speed synchronous CPU wherein the CPU clock is independent of the memory controller clock. The CPU clock is connected to both the CPU and a control interface state tracker located externally to the memory controller. The control int ...


8
Thomas F Heil, Edward A McDonald, Gene F Young: Method and apparatus for transferring data within a computer system. NCR Corporation, Jack R Penrod, Paul J Maginot, December 7, 1993: US05269005 (28 worldwide citation)

In a processing system any response to an interrupt acknowledge cycle is deferred until the transfer of buffered data to be written from an agent on a subsystem I/O bus to main memory of the system is assured. To expedite system operation, data to be written to main memory by an agent on an I/O bus ...


9
Thomas F Heil, Edward A McDonald, Gene F Young, Craig A Walrath, James M Ottinger, Marti D Miller: Retry scheme for controlling transactions between two busses. NCR Corporation, James M Stover, May 23, 1995: US05418914 (26 worldwide citation)

A retry scheme for optimizing use of a first bus in a computer system which includes a plurality of bus masters connected through the first bus to an interface circuit and second bus. The interface circuit includes logic for generating a busy signal when the second bus is in a busy state and logic f ...


10
Thomas F Heil: Peripheral component interconnect special cycle protocol using soft message IDS. AT&T Global Information Solutions Company, George H Gates, April 9, 1996: US05507002 (24 worldwide citation)

A Peripheral Component Interconnect (PCI) bus provides component level interconnection of processors, peripherals and memories. A bus protocol mechanism includes a Special Cycle command for defining "soft", i.e., configurable, transaction types for use between devices communicating on the PCI bus. U ...