Arthur J Beaverton, Thomas E Hunt: System for updating program stored in EEPROM by storing new version into new location and updating second transfer vector to contain starting address of new version. Digital Equipment Corporation, Kenyon & Kenyon, May 11, 1993: US05210854 (235 worldwide citation)

Firmware resident in electrically erasable programmable read only memory ("EEPROM") can be updated by a user while maintaining the intelligence of a computer system during the updating process by a control logic device. The control logic device decodes address and control signals to provide a hardwa ...

James R Duval, Thomas E Hunt, Kevin R Peterson: Configurable data path arrangement for resolving data type incompatibility. Digital Equipment Corporation, Cesari and McKenna, November 9, 1993: US05261077 (32 worldwide citation)

Apparatus for sharing data between processors having certain incompatible data formats is provided. A configurable data path unit and an address mapping unit allow a peripheral processor to access addressable storage locations within a host processor's main memory and store data types in a format so ...

Authur J Beaverson, Thomas E Hunt, Gary P Lidington: Programmable stall cycles. Digital Equipment Corporation, Kenyon & Kenyon, January 18, 1994: US05280608 (5 worldwide citation)

A system and method for testing a computing system by introducing stall cycles at an arbiter that controls access to a bus that is commonly used by the CPU and I/O devices for stressing the computing system with regard to the latency and bandwidth.

Stephen F Shirron, Ralph O Weber, Thomas E Hunt: Microprocessor system for selectively accessing a processor internal register when the processor has control of the bus and partial address identifying the register. Digital Equipment Corporation, Arthur W Fisher, Denis G Maloney, Mark J Casey, April 18, 1995: US05408612 (5 worldwide citation)

An apparatus which allows for software sharing between multiple controllers includes a computer bus and a plurality of processors each having input and output ports coupled to the bus. Each processor also has at least one internal storage register. The apparatus further includes means, which are res ...