1
Theodore O Meyer, John W Mosier II, Douglas A Pike Jr, Theodore G Hollinger, Dah W Tsang: Method of making topographic pattern delineated power MOSFET with profile tailored recessed source. Advanced Power Technology, Marger Johnson McCollom & Stolowitz, May 28, 1991: US05019522 (54 worldwide citation)

A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the ...


2
Theodore O Meyer, John W Mosier II, Douglas A Pike Jr, Theodore G Hollinger: Iopographic pattern delineated power mosfet with profile tailored recessed source. Advanced Power Technology, Marger & Johnson, January 23, 1990: US04895810 (52 worldwide citation)

A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the ...


3
Theodore O Meyer, John W Mosier II, Douglas A Pike Jr, Theodore G Hollinger, Dah W Tsang: Topographic pattern delineated power MOSFET with profile tailored recessed source. Advanced Power Technology, Marger Johnson McCollom & Stolowitz, September 3, 1991: US05045903 (46 worldwide citation)

A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the ...


4
Theodore G Hollinger: Mask-surrogate semiconductor process employing dopant protective region. Advanced Power Technology, Kolisch Hartwell & Dickinson, May 31, 1988: US04748103 (19 worldwide citation)

A mask-defect-immune process for making MOS semiconductor devices. The process features the creation of a surrogate mask in semiconductor wafer material per se, thus to eliminate the requirement that plural masks be used, and that plural mask alignments be performed. In all ways of practicing the in ...


5
Theodore G Hollinger: Frequency-dependent single-phase to three-phase AC power conversion. APC Onsite, Kolisch Hartwell & Dickinson, February 6, 1990: US04899268 (19 worldwide citation)

Apparatus for supplying from a single-phase, known-frequency AC source, three-phase AC power at the same frequency. The apparatus features circuitry which employs high-speed power switching with respect to only one phase of a three-phase load, with the result that only two high-speed power-switching ...


6
Theodore G Hollinger: Frequency-independent single-phase to three-phase AC power conversion. APC Onsite, Kolisch Hartwell & Dickinson, March 13, 1990: US04908744 (15 worldwide citation)

Three-phase power-conversion wherein the frequency output voltage is independent of the frequency of input voltage. One of three input terminals in a load powered by the apparatus is directly grounded. Each of the other two input terminals is supplied a sinusoidal voltage artifact from an appropriat ...


7
Theodore G Hollinger: Mask surrogate semiconductor process with polysilicon gate protection. Advanced Power Technology, Marger Johnson McCollom & Stolowitz, October 26, 1993: US05256583 (12 worldwide citation)

A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the ...


8
Theodore G Hollinger: Mask surrogate semiconductor process employing dopant-opaque region. Advanced Power Technology, Marger Johnson McCollom & Stolowitz, February 18, 1992: US05089434 (11 worldwide citation)

A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the ...


9
Theodore G Hollinger: Semiconductor doping process. August 23, 1988: US04766094 (4 worldwide citation)

A method for making a semiconductor device, such as a power-MOS transistor, wherein dopant is introduced into the structure underlying a lead contact pad to create a conducting subregion which minimizes electrical conductive breakdown.


10
Theodore G Hollinger: Method for controlling electrical breakdown in semiconductor power devices. Sundstrand Corporation, Marger Johnson McCollom & Stolowitz, July 18, 1995: US05434095 (3 worldwide citation)

A field-effect, power-MOS transistor wherein a region under the gate contact pad is specially doped with a dopant that is electrically compatible with that in the transistor's channel to obviate problems of electrical breakdown in that region.