1
Thang Tran: Method and apparatus for a self-timed and self-enabled distributed clock. Thang Tran, Akin Gump Strauss Hauer & Feld L, November 16, 1999: US05987620 (60 worldwide citation)

A self-timed and self-enabled distributed clock is provided for pipeline processor design having functional blocks which include one or more pipeline stages for processing instructions and operations. Each pipeline stage of the processor includes self-timed logic and an enable signal to set up the v ...


2
Thang Tran: Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture. Texas Instruments Incorporated, Wade J Brady III, Frederick J Telecky Jr, February 15, 2011: US07890735 (42 worldwide citation)

A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute pipelines (1740, 1750), and coupling circuitry (1916) operable in a first mode to couple first and second thr ...


3
Rupaka Mahalingaiah, Thang Tran: Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction. Advanced Micro Devices, Lawrence J Merkel, B Noel Kivlin, Conley Rose & Tayon, November 9, 1999: US05983337 (32 worldwide citation)

A superscalar microprocessor implements instruction level patching. A instruction fetch unit includes a register for storing opcodes of instructions to be patched. When an instruction is fetched, the instruction fetch unit compares the opcode of the fetched instruction to the opcode stored in the pa ...


4
Thang Tran: Combination prefetch buffer and instruction cache. Advanced Micro Devices, Jenkens & Gilchrist P C, December 17, 1996: US05586295 (25 worldwide citation)

A cache memory system features a combination instruction cache and prefetch buffer, which obviates any requirement for a bus interconnecting the cache and buffer and which also effectively allows the instruction buffer to write data into the cache with improved utilization of prefetched instructions ...


5
William M Johnson, David B Witt, Thang Tran: High speed instruction alignment unit for aligning variable byte-length instructions according to predecode information in a superscalar microprocessor. Advanced Micro Devices, B Noel Kivlin, Conley Rose & Tayon, May 26, 1998: US05758114 (22 worldwide citation)

An instruction alignment unit is provided which transfers a fixed number of instructions from an instruction cache to each of a plurality of decode units. The instructions are selected from a quantity of bytes according to a predecode tag generated by a predecode unit. The predecode tag includes sta ...


6
Lynda Vaughan, Chris Robertson, Helen Kerr, Tysen Lee, Graham Sharples, Sophie Nicol, Johnny Lim, Thang Tran: Security device for a workstation. Roblinc Solutions, Kerr & Company, Bereskin & Parr, February 10, 2004: US06689954 (17 worldwide citation)

A security device for attaching laptop computers and the like to a desk includes a body portion which is to be received in an aperture of the work surface of a work station or desk. The body portion includes a grommet which fits within the aperture with a flange at the top. A lock plate bears agains ...


7
Thang Tran, David B Witt: High performance superscalar alignment unit. Advanced Micro Devices, B Noel Kivlin, Conley Rose & Tayon PC, November 3, 1998: US05832249 (16 worldwide citation)

An instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of decode units which form fixed issue positions within a superscalar microprocessor. The instruction alignment unit may be implemented with a relatively small number ...


8
Thang Tran, David B Witt: High performance superscalar alignment unit. Advanced Micro Devices, B Noel Kivlin, Lawrence J Merkel, Conley Rose & Tayon PC, December 21, 1999: US06006324 (12 worldwide citation)

An instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of decode units which form fixed issue positions within a superscalar microprocessor. The instruction alignment unit may be implemented with a relatively small number ...


9
Thang Tran: Branch prediction and other processor improvements using FIFO for bypassing certain processor pipeline stages. Texas Instruments Incorporated, Wade James Brady III, Frederick J Telecky Jr, February 5, 2008: US07328332 (12 worldwide citation)

A processor (1700) including a pipeline (1710, 1740) having a fetch pipeline (1710) with branch prediction circuitry (1840) to supply respective predicted taken target addresses for branch instructions, an execution pipeline (1740) with a branch execution circuit (1870), and storage elements (in 186 ...


10
David B Witt, Thang Tran: Superscalar microprocessor including an instruction alignment unit with limited dispatch to decode units. Advanced Micro Devices, B Noel Kivlin, Conley Rose & Tayon, October 6, 1998: US05819057 (11 worldwide citation)

A high performance superscalar microprocessor including an instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of decode units which form fixed issue positions within the superscalar microprocessor. The instruction alignm ...