1
Toru Baji, Yukio Nakano, Shiro Tanabe, Tetsuya Nakagawa, Hirotsugu Kojima: Multimedia bidirectional broadcast system. Hitachi, Pennie & Edmonds, June 25, 1991: US05027400 (738 worldwide citation)

A multimedia bidirectional broadcast system including a broadcast station and subscriber terminals. The broadcast station includes a main control unit having therein a data base control table in which program and commerical down load sequences are recorded depending on a setting effected by a subscr ...


2
Tetsuya Nakagawa: Obstacle detection apparatus for vehicles. Mitsubishi Denki Kabushiki Kaisha, Sughrue Mion Zinn Macpeak & Seas, April 28, 1998: US05745050 (158 worldwide citation)

An obstacle detecting apparatus including a light projecting assembly for projecting the laser light generated in a laser light emitting element through a light emitting path, a light introducing assembly for introducing the laser light reflected by an obstacle into a light receiving element through ...


3
Tetsuya Nakagawa, Masafumi Kunori: Radio communication semiconductor integrated circuit, data processing semiconductor integrated circuit and portable device. Renesas Technology, Mattingly Stanger Malur & Brundidge P C, October 28, 2008: US07444168 (88 worldwide citation)

A portable device having a communication function composed of a plurality of LSIs operated in synchronization with a clock, such as a baseband LSI and a logic LSI such as an application processor, can synchronize the baseband LSI with the logic LSI without lowering the performance of the logic LSI.


4
Toru Baji, Kouki Noguchi, Tetsuya Nakagawa, Motonobu Tonomura, Hajime Akimoto, Toshiaki Masuhara: Apparatus including a pair of neural networks having disparate functions cooperating to perform instruction recognition. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, June 20, 1995: US05426745 (68 worldwide citation)

There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for rec ...


5
Hiroko Sukeda, Yoshiyuki Kaneko, Tetsuya Nakagawa, Muneaki Yamaguchi, Toshihisa Tsukada: Electronic interpreter utilizing linked sets of sentences. Hitachi, Antonelli Terry Stout & Kraus, December 29, 1998: US05854997 (62 worldwide citation)

An electronic interpreter for interpreting sentences between a first person and a second person. The electronic interpreter includes a memory for storing sentence data in a data structure having a plurality of sets of sentences including translations of the sentences, wherein each sentence of each s ...


6
Takao Watanabe, Tetsuya Nakagawa, Yoshinobu Nakagome: Parallel processor having decoder for selecting switch from the group of switches and concurrently inputting MIMD instructions while performing SIMD operation. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, July 9, 1996: US05535410 (56 worldwide citation)

A parallel processor utilizing a memory cell array for rapidly performing parallel processing by switching between SIMD and MIMD operations depending on the type of problems to be solved. Where SIMD and MIMD operations are mixed in an application, the time loss in the switching therebetween is elimi ...


7
Toru Baji, Kouki Noguchi, Tetsuya Nakagawa, Motonobu Tonomura, Hajime Akimoto, Toshiaki Masuhara: Customized personal terminal device. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, November 10, 1992: US05163111 (50 worldwide citation)

There is provided a customized personal terminal device capable of operating in response to input data peculiar to the operator, comprising a speech recognition unit for recognizing inputted speech, an image recognition unit for recognizing inputted image, and an instruction recognition unit for rec ...


8
Atsushi Kiuchi, Tetsuya Nakagawa: System with loop buffer and repeat control circuit having stack for storing control information. Hitachi, Antonelli Terry Stout & Kraus, November 26, 1996: US05579493 (43 worldwide citation)

A low-power data processor in which memory access for reading out an instruction module to be repeatedly executed is controlled to decrease the power consumption of the data processor. The data processor comprises an instruction buffer formed of, for example, a CMOS device operable with low power co ...


9
Tetsuya Nakagawa, Atsushi Kiuchi: Double precision division circuit and method for digital signal processor. Hitachi America, Flehr Hohbach Test Albritton & Herbert, June 20, 1995: US05426600 (39 worldwide citation)

An arithmetic operation execution unit includes a plurality of 2N bit data registers and an arithmetic logic unit (ALU). The execution unit is coupled to data busses each having a data path width of N bits for transferring data to and from the data registers. An XOR gate and inverter gate are provid ...


10
Takao Watanabe, Yoshinobu Nakagome, Kazuo Ishikura, Tetsuya Nakagawa, Atsushi Kiuchi: Semiconductor IC with a plurality of processing circuits which receive parallel data via a parallel data transfer circuit. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, December 29, 1998: US05854636 (37 worldwide citation)

A semiconductor integrated circuit having a two-dimensional array (MAR) and a parallel data transfer circuit (TRC) for transferring from the array data read out in parallel through data lines, in parallel to a processing circuit group (PE) by selecting the word lines of the two-dimensional memory ar ...



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