1
Tetsuhiko Okada, Osamu Nishii, Hiroshi Takeda: Method for prefetching pointer-type data structure and information processing apparatus therefor. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, July 29, 1997: US05652858 (58 worldwide citation)

In order to allow prefetching of pointer-type data structure, an instruction word of load instruction has pointer hints indicating that the data being loaded by the instruction comprises a pointer specifying the address of the next data. When a CPU executes such an instruction, and the data requeste ...


2
Tetsuhiko Okada, Naoki Hamanaka, Naohiko Irie, Takehisa Hayashi, Tetsuya Mochida, Masabumi Shibata, Youichi Tanaka, Yasuhiro Ishii: Multi-processor system and its network. Hitachi, Beall Law Offices, January 4, 2000: US06011791 (24 worldwide citation)

In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the follow ...


3
Susumu Narita, Fumio Arakawa, Tetsuhiko Okada, Kunio Uchiyama: Microprocessor capable of decoding two instructions in parallel. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, April 18, 1995: US05408625 (17 worldwide citation)

An instruction fetch unit IU in a microprocessor capable of decoding two instructions in parallel fetches first and second instructions of the shortest instructions in one cycle. The fetched first instruction is supplied to and decoded by a first instruction decoder ID0, while the fetched second ins ...


4
Susumu Narita, Makoto Hanawa, Tadahiko Nishimukai, Tetsuhiko Okada: Pipeline processor with prefetch circuit. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, September 15, 1992: US05148532 (16 worldwide citation)

In a pipeline processing microprocessor, an instruction fetch unit is keyed to the formation or nonformation of a conditional branch micro-instruction result to determine the subsequent macro-instruction to be fetched from an external memory or cache. A macro-instruction is first decoded in an instr ...


5
Tetsuhiko Okada, Naoki Hamanaka, Naohiko Irie, Takehisa Hayashi, Tetsuya Mochida, Masabumi Shibata, Youichi Tanaka, Yasuhiro Ishii: Multi-processor system and its network. Hitachi, Mattingly Stanger & Malur P C, April 27, 2004: US06728258 (14 worldwide citation)

In a multi-processor system interconnecting processor units, memory units, and input/output units connected to input/output devices via a crossbar switch having a plurality of ports, the transmitter of each processor unit has a circuit for determining a destination of an access request in the follow ...


6
Yuji Tsushima, Hideya Akashi, Keitaro Uehara, Naoki Hamanaka, Toru Shonai, Tetsuhiko Okada, Masamori Kashiyama: Multiprocessor system and methods for transmitting memory access transactions for the same. Hitachi, Antonelli Terry Stout & Kraus, February 4, 2003: US06516391 (13 worldwide citation)

In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, name ...


7
Tetsuhiko Okada, Hideki Murayama, Takehisa Hayashi, Atsushi Ugajin, Yasuhiro Ishii, Masahiro Kitano: Input/output control method and data processor. Hitachi, Fay Sharpe Beall Fagan Minnich & McKee, October 14, 1997: US05678062 (11 worldwide citation)

A system for controlling the DMA transfer for a plurality of IO devices has an IO controller for each group of the IO devices. Data is retrieved from memory and stored in the IO controller where it is analyzed. The retrieved data has a structure that permits a group of DMA start request quads to be ...


8
Osamu Nishii, Nobuyuki Hayashi, Noriharu Hiratsuka, Tetsuhiko Okada, Hiroshi Takeda: Memory system performing fast access to a memory location by omitting transfer of a redundant address. Hitachi, Antonelli Terry Stout & Kraus, February 16, 1999: US05873122 (10 worldwide citation)

A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address reg ...


9
Nobukazu Kondo, Seiji Kaneko, Hideaki Gemma, Tetsuhiko Okada, Kazuhiko Komori, Koichi Okazawa: Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment. Hitachi, Antonelli Terry Stout & Kraus, June 27, 1995: US05428753 (7 worldwide citation)

An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the ...


10
Nobukazu Kondo, Seiji Kaneko, Hideaki Gemma, Tetsuhiko Okada, Kazuhiko Komori, Koichi Okazawa: Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment. Hitachi, Antonelli Terry Stout & Kraus, August 12, 1997: US05657458 (6 worldwide citation)

An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the ...