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Terry L Biggs, Antonio A Lagana: Data processor having a cache memory capable of being used as a linear ram bank. Motorola, Charlotte B Whitaker, April 25, 1995: US05410669 (68 worldwide citation)

A data processing system (10) having a dual purpose memory (14) comprising multiple cache sets. Each cache set can be individually configured as either a cache set or as a static random access memory (SRAM) bank. Based upon the configuration of the set, the tag store array (58) is used for storage o ...


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Terry L Biggs, Donald L Tietjen, Jesse R Wilson: Method and apparatus for providing both power and control by way of an integrated circuit terminal. Motorola, Susan C Hill, July 9, 1996: US05535398 (11 worldwide citation)

A method and apparatus for providing both power and control by way of an integrated circuit terminal (22). In one form, a clock source (12) supplies a periodic signal to a phase lock loop circuit (32) and to a multiplexer (34). The output of the phase lock loop circuit (32) is a second input to the ...


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John Michael Hudson, Donald L Tietjen, Terry L Biggs: System and method for recovering a microprocessor from a locked bus state. Motorola, Bruce E Hayden, M Kathryn Tsirigotis, October 5, 1999: US05961622 (9 worldwide citation)

A data processing system (10) and method is used to recover a CPU from faulty operation. A single timer (38) is used to enable recovery operations. When the timer (38) experiences a first time-out event, a software watchdog interrupt (28) is generated. If the software interrupt (28) is properly hand ...


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Donald L Tietjen, Terry L Biggs: Synchronous memory interface. Motorola, Daniel D Hill, June 29, 1999: US05917761 (7 worldwide citation)

A synchronous memory interface feeds back a buffered (34) clock signal to a microcontroller (20) to simplify and improve output hold time for the memory (38). An output delay circuit (36) in the microcontroller (20) is controlled by the same delayed clock signal as the synchronous memory (38). This ...


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Terry L Biggs, Antonio A Lagana: A data processor having a cache memory capable of being used as a linear ram bank. Motorola, January 21, 1995: TW239200

A data processing system (10) having a dual purpose memory (14) ?comprising multiple cache sets. Each cache set can be ?individually configured as either a cache set or as a static ?random access memory (SRAM) bank. Based upon the configuration of ?the set, the tag store array (58) is used for stora ...


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