1
Kangguo Cheng, Balasubramanian S Haran, Shom Ponoth, Theodorus E Standaert, Tenko Yamashita: Bulk fin-field effect transistors with well defined isolation. International Business Machines Corporation, Jose Gutman, Fleit Gibbons Gutman Bongini & Bianco PL, April 16, 2013: US08420459 (29 worldwide citation)

A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer ...


2
Veeraraghavan S Basker, Huiming Bu, Kangguo Cheng, Balasubramanian S Haran, Nicolas Loubet, Shom Ponoth, Stefan Schmitz, Theodorus E Standaert, Tenko Yamashita: Cut-very-last dual-epi flow. International Business Machines Corporation, Harrington & Smith, October 29, 2013: US08569152 (20 worldwide citation)

A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered por ...


3
Takashi Ando, Josephine B Chang, Sivananda K Kanakasabapathy, Pranita Kulkarni, Theodorus E Standaert, Tenko Yamashita: FinFET parasitic capacitance reduction using air gap. International Business Machines Company, Harrington & Smith, January 28, 2014: US08637930 (19 worldwide citation)

A transistor, for example a FinFET, includes a gate structure disposed over a substrate. The gate structure has a width and also a length and a height defining two opposing sidewalls of the gate structure. The transistor further includes at least one electrically conductive channel between a source ...


4
Takashi Ando, Josephine B Chang, Sivananda K Kanakasabapathy, Pranita Kulkarni, Theodorus E Standaert, Tenko Yamashita: FinFET parasitic capacitance reduction using air gap. International Business Machines Corporation, Harrington & Smith, January 28, 2014: US08637384 (16 worldwide citation)

Methods are disclosed to fabricate a transistor, for example a FinFET, by forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of the channel, the gate structure having a width and a l ...


5
Veeraraghavan S Basker, Huiming Bu, Effendi Leobandung, Theodorus E Standaert, Tenko Yamashita, Chun Chen Yeh: SOI FinFET with recessed merged Fins and liner for enhanced stress coupling. International Business Machines Corporation, Cantor Colburn, Vazken Alexanian, May 21, 2013: US08445334 (15 worldwide citation)

FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SOI substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the ...


6
Veeraraghavan S Basker, Andres Bryant, Huiming Bu, Wilfried Haensch, Effendi Leobandung, Chung Hsun Lin, Theodorus E Standaert, Tenko Yamashita, Chun chen Yeh: Method for fabricating finFET with merged fins and vertical silicide. International Business Machines Corporation, Stephen Bongini, Fleit Gibbons Gutman Bongini & Bianco PL, June 4, 2013: US08455313 (13 worldwide citation)

A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack incl ...


7
Tenko Yamashita: Silicon-on-insulator (SOI) substrate having dual surface crystallographic orientations and method of forming same. Sony Corporation, Sony Electronics, Mayer Fortkort & Williams PC, Stuart H Mayer Esq, September 27, 2005: US06949420 (12 worldwide citation)

A method is provided of forming a silicon-on-insulator (SOI) substrate having at least two exposed surface crystal orientations. The method begins by providing an SOI substrate having a first silicon layer with a surface having a first crystal orientation located on a first buried oxide layer. The b ...


8
Kangguo Cheng, Balasubramanian S Haran, Shom Ponoth, Theodorus E Standaert, Tenko Yamashita: MOS capacitors with a finfet process. International Business Machines Corporation, Tutunjian & Bitetto P C, Vazken Alexanian, November 12, 2013: US08581320 (12 worldwide citation)

Capacitors include a first electrical terminal that has fins formed from doped semiconductor on a top layer of doped semiconductor on a semiconductor-on-insulator substrate; a second electrical terminal that has an undoped material having bottom surface shape that is complementary to the first elect ...


9
Veeraraghavan S Basker, Chun chen Yeh, Tenko Yamashita: Strained silicon nFET and silicon germanium pFET on same wafer. International Business Machines Corporation, Thomas Grzesik, Fleit Gibbons Gutman Bongini & Bianco PL, September 23, 2014: US08841178 (12 worldwide citation)

Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a dielectric layer, and a semiconductor layer including silicon germanium (SiGe). At least one SiGe fin is formed ...


10
Veeraraghavan S Basker, Bruce Doris, Ali Khakifirooz, Tenko Yamashita, Chun chen Yeh: Forming strained and relaxed silicon and silicon germanium fins on the same wafer. International Business Machines Corporation, Fleit Gibbons Gutman Bongini & Bianco PL, Thomas Grzesik, February 10, 2015: US08951870 (11 worldwide citation)

Various embodiments form strained and relaxed silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is formed. The semiconductor wafer comprises a substrate, a dielectric layer, and a strained silicon germanium (SiGe) layer. At least one region of the s ...



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