1
Te Long Chiu: Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof. June 4, 1991: US05021848 (89 worldwide citation)

The EEPROM has the selection device in series with the memory device having a floating gate disposed over the channel between the buried drain and the buried source, and insulated from the channel by 200 A to 1000 A of gate oxide, an add-on floating gate shorted electrically to the floating gate, an ...


2
Daniel C Guterman, Te Long Chiu: Self-limiting erasable memory cell with triple level polysilicon. Texas Instruments Incorporated, John G Graham, November 24, 1981: US04302766 (80 worldwide citation)

A non-volatile semiconductor memory device of the electrically erasable type employs a floating gate which is programmed by application to high voltage across the source and drain so that hot electrons traverse the gate oxide. The floating gate is discharged by electron tunneling through an erase wi ...


3
Te Long Chiu, Jih Chang Lien: Electrically programmable floating gate semiconductor memory device. Texas Instruments Incorporated, John G Graham, March 15, 1983: US04376947 (66 worldwide citation)

An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the ...


4
Te Long Chiu: Method of fabricating an MOS memory array having electrically-programmable and electrically-erasable storage devices incorporated therein. SEEQ Technology, Lyon & Lyon, January 1, 1985: US04490900 (57 worldwide citation)

A method for fabricating an MOS memory array is disclosed, wherein the method includes steps for constructing electrically-programmable and electrically-erasable memory cells (2, 198, 200) in combination with assorted peripheral devices (202, 204, 206) on a semiconductor substrate (8, 71). Tunneling ...


5
Jih Chang Lien, Te Long Chiu: Interlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline silicon. Texas Instruments Incorporated, John G Graham, February 1, 1983: US04370798 (39 worldwide citation)

Integrated circuit resistor elements ideally suited for load devices in static MOS RAM cells are made in second-level polycrystalline silicon by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The second-level polysilicon is insulated from first-level polysilicon b ...


6
Te Long Chiu, Jih Chang Lien: Electrically programmable floating gate semiconductor memory device. Texas Instruments Incorporated, John G Graham, August 21, 1984: US04467453 (37 worldwide citation)

An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the ...


7
Te Long Chiu: Electrically-flash-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area. May 28, 1991: US05019879 (33 worldwide citation)

The flash EEPROM memory device with the floating gate that is over the channel area and insulated from the channel by 200 to 1000 A of gate oxide, and that is also over the thin tunnel dielectric area at the source and insulated from the source by 70 A to 200 A of tunnel dielectric. Another improvem ...


8
Te Long Chiu, Jih Chang Lien: Electrically programmable floating gate semiconductor memory device. Texas Instruments Incorporated, John G Graham, May 7, 1985: US04514897 (23 worldwide citation)

An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the ...


9
Te Long Chiu: Non-volatile dynamic random access memory array and the method of fabricating thereof. August 18, 1992: US05140551 (16 worldwide citation)

The present invention relates to a non-volatile dynamic random acess memory cell having a dynamic random access memory cell and an electrically-erasable and electrically-programmable memory device connected on the opposite sides of an insolation device. It also relates to a memory array of the non-v ...


10
Joseph G Nolan, Michael A Van Buskirk, Te Long Chiu, Ying K Shum: Electrically alterable non-volatile memory device. Sierra Semiconductor Corporation, Limbach Limbach & Sutton, October 25, 1988: US04780750 (14 worldwide citation)

In this invention, an Electrically Alterable Non-Volatile Memory (EANOM) cell is disclosed. The EANOM ceil comprises an MOS transistor, having a source, a gate and a drain. The EANOM cell also has a two-terminal tunnel device, one end of which is connected to the gate of the MOS transistor. The othe ...