1
Taylor R Efland, Dave Cotton, Dale J Skelton: ESD protection structure using LDMOS diodes with thick copper interconnect. Texas Instruments Incorporated, Mark E Courtney, W James Brady III, Richard L Donaldson, November 21, 1995: US05468984 (167 worldwide citation)

An interconnection structure and method for a multiple zener diode ESD protectoin circuit for power semiconductor devices. A plurality of lateral Zener diodes is formed. Each device is formed of a plurality of cathode and anode diffusion regions to be coupled together to form the cathode and anode o ...


2

3
Taylor R Efland, Quang X Mai, Charles E Williams, Stephen A Keller: Thick plated interconnect and associated auxillary interconnect. Texas Instruments Incorporated, Peter K McLarty, W James Brady III, Richard L Donaldson, February 1, 2000: US06020640 (86 worldwide citation)

A thick plated interconnect (80) comprising a copper lead (50) and a bonding cap (84) coupled to the copper lead (50). The bonding cap (84) may include a bondable member (86) formed from a bondable layer (62) comprising aluminum. A barrier member (88) may be formed from a barrier layer (60). The bar ...


4

5
Satwinder Malhi, Taylor R Efland, Oh Kyong Kwon: Triple diffused lateral resurf insulated gate field effect transistor compatible with process and method. Texas Instruments Incorporated, Jacqueline J Garner, Richard L Donaldson, William E Hiller, September 13, 1994: US05346835 (67 worldwide citation)

A triple-diffused lateral RESURF transistor (55,57) uses a threshold voltage adjust implant (52, 54) in conjunction with a thinner gate oxide (64) to yield a device which is more compatible with CMOS VLSI manufacturing processes and which delivers better performance characteristics than more convent ...


6
Taylor R Efland, Quang X Mai, Charles E Williams, Stephen A Keller: Method of forming improved thick plated copper interconnect and associated auxiliary metal interconnect. Texas Instruments Incorporated, W James Brady III, Richard L Donaldson, February 15, 2000: US06025275 (51 worldwide citation)

A thick plated interconnect (80) may be fabricated by forming a metal layer (20) above a semiconductor layer (12). A dielectric layer (22) may be formed on the metal layer (20). A via (24) may be formed in the dielectric layer (22) to expose the metal layer (20). A copper lead (50) may be formed ele ...


7

8
Philip L Hower, Taylor R Efland: N-channel LDMOS with buried p-type region to prevent parasitic bipolar effects. Texas Instruments Incorporated, Peter K McLarty, W James Brady III, Frederick J Telecky Jr, October 25, 2005: US06958515 (45 worldwide citation)

An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly ...


9
Taylor R Efland, David Cotton, Dale J Skelton: Multiple transistor integrated circuit with thick copper interconnect. Texas Instruments Incorporated, Mark E Courtney, W James Brady III, Richard L Donaldson, January 12, 1999: US05859456 (42 worldwide citation)

An interconnection structure and method for a multiple transistor integrated circuit power device is disclosed. A power integrated circuit is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain of multiple LDMOS transistors. Each diffusion ...


10
Oh Kyong Kwon, Taylor R Efland, Satwinder Malhi, Wai T Ng: Lateral double diffused insulated gate field effect transistor fabrication process. Texas Instruments Incorporated, Jacqueline J Garner, William E Hiller, Richard L Donaldson, April 26, 1994: US05306652 (37 worldwide citation)

A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12) . A thick insulator laye ...



Click the thumbnails below to visualize the patent trend.