1
Takehide Shirato, Teruo Tazunoki: Semiconductor device. Fujitsu, Armstrong Nikaido Marmelstein Kubovcik & Murray, April 3, 1990: US04914503 (75 worldwide citation)

A semiconductor device comprises a semiconductor chip having main power supply lines which are arranged in peripheral regions in the vicinity of edges of the semiconductor chip and which are formed with multi-level metallization. The main power supply lines are formed with arrangements in that layer ...


2
Takehide Shirato, Nobuhiko Aneha: Semiconductor device having a silicon on insulator structure. Fujitsu, Armstrong Nikaido Marmelstein & Kubovcik, February 28, 1989: US04809056 (65 worldwide citation)

A semiconductor device having an SOI structure comprises an insular single crystal silicon body formed on an insulator layer, a first region of a first type semiconductor and source and drain regions of a second type semiconductor provided in the insular single crystal silicon body so that the first ...


3
Takehide Shirato: Method of forming conductive channel extensions to active device regions in CMOS device. Fujitsu, Staas & Halsey, July 23, 1985: US04530150 (63 worldwide citation)

A method for producing a semiconductor device which includes forming, in a well having the first conductivity type and selectively provided in a semiconductor substrate having a second conductivity type opposite the first conductivity type, two first impurity diffusion regions having the second cond ...


4
Takehide Shirato, Taiji Ema: Method for fabricating an insulated-gate FET having a narrow channel width. Fujitsu, Staas & Halsey, April 12, 1988: US04737471 (36 worldwide citation)

A method of fabricating a narrow channel width IG-FET which includes compensating for impurities diffused into the channel region from the channel stopper, thereby providing the IG-FET with a threshold providing the IG-FET with a threshold voltage establishing at a level substantially the same as th ...


5
Takehide Shirato: Protection element for semiconductor device. Fujitsu, Staas & Halsey, July 22, 1986: US04602267 (34 worldwide citation)

A protection element responsible for protecting a semiconductor element included in a semiconductor device from a voltage higher than the voltage which the semiconductor element is allowed to receive, the protection element virtually being a lateral bipolar transistor, in which an improvement is mad ...


6
Takehide Shirato, Shinichi Sekine: Protection device in an integrated circuit. Fujitsu, Armstrong Nikaido Marmelstein & Kubovcik, December 1, 1987: US04710791 (25 worldwide citation)

An I/O protection device which protects the IC from noise especially from static charge break down is disclosed. A resistance body made from polysilicon is provided between the I/O pad and I/O circuit of the IC. The resistance body may be formed over the gate oxide or field oxide layer. Beneath the ...


7
Takehide Shirato: Mask ROM-type semiconductor memory device. Fujitsu, Staas & Halsey, February 19, 1985: US04500975 (25 worldwide citation)

A plurality of MIS-type transistors are arranged in a matrix, with each one of these MIS-type transistors corresponding to one memory information bit. These MIS-type transistors are formed so as to store and read binary information in accordance with whether the characteristic of these MIS-type tran ...


8
Takehide Shirato: Semiconductor device having a protection circuit with lateral bipolar transistor. Fujitsu, Staas & Halsey, January 19, 1988: US04720737 (22 worldwide citation)

A protection circuit for inner elements such as metal insulator semiconductor (MIS) field effect transistors in a semiconductor device of high packing density has been improved. The protection circuit comprises protective elements of two types. One type has a deep diffusion region providing the elem ...


9
Takehide Shirato: Process for producing a semiconductor device. Fijitsu, Staas & Halsey, September 14, 1982: US04348802 (15 worldwide citation)

In a process for producing a semiconductor device, particularly an MIS structure semiconductor device, an electrode, which is in ohmic contact with the semiconductor substrate, is usually formed on the surface which is opposite to the surface having MIS FETs. However, in a recently developed process ...


10
Takehide Shirato: Complementary semiconductor device having high switching speed and latchup-free capability. Fujitsu, Armstrong Nikaido Marmelstein Kubovcik & Murray, January 9, 1990: US04893164 (14 worldwide citation)

A complementary type semiconductor device comprises n-channel FETs and three types of p-channel FETs formed in an n.sup.- -type semiconductor substrate. First p-channel FETs and n-channel FETs, both having deep well regions are used for input/output circuits disposed in peripheral areas of the subst ...