1
Toru Watabe, Yasutomo Sakurai, Takumi Kishino, Yoshio Hirose, Koichi Odahara, Kazuhiro Nonomura, Takumi Takeno, Shinya Katoh, Takato Noda: Information processing system. Fujitsu, Staas & Halsey, November 10, 1998: US05835697 (23 worldwide citation)

A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processo ...


2
Toru Watabe, Yasutomo Sakurai, Takumi Kishino, Yoshio Hirose, Koichi Odahara, Kazuhiro Nonomura, Takumi Takeno, Shinya Katoh, Takato Noda: Information processing system. Fujitsu, Staas & Halsey, June 6, 2000: US06073249 (15 worldwide citation)

A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processo ...


3
Takayuki Shimamura, Shinya Kato, Takato Noda, Takumi Nonaka: Cache-tag control method in information processing apparatus having cache, with error checking mechanism in cache tag, and information processing apparatus using this control method. Fujitsu, Staas & Halsey, January 20, 2004: US06681299 (12 worldwide citation)

To provide a cache-tag control method capable of correcting an error and capable of keeping a high-speed operation of a system at the same time. A true-tag with a parity code attached and a shadow-tag having an inverted polarity of the true-tag are stored respectively in separate addresses within a ...


4
Takaharu Ishizuka, Takato Noda, Yasuhide Shibata, Takumi Takeno, Katsunori Takeshita, Fumitake Sugano: Information processing system in which memory devices and copies of tags are accessed in response to access requests issued from plurality of processing units. Fijitsu, Staas & Halsey, September 18, 2001: US06292870 (3 worldwide citation)

Processing units each having a first memory and a system controller are interconnected over a bus. The system controller includes access control units for controlling access to copies of tags of the first memories in the processing units and access to second memories to which a plurality of ways lea ...