1
Takao Akaogi, Lee Edward Cleveland, Kendra Nguyen: Multiple bank simultaneous operation for a flash memory. Advanced Micro Devices, Fujitsu, Brinks Hofer Gilson & Lione, May 29, 2001: US06240040 (159 worldwide citation)

An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write ope ...


2
Johnny C Chen, Chung K Chang, Tiao Hua Kuo, Takao Akaogi: Bank architecture for a non-volatile memory enabling simultaneous reading and writing. Fliesler Dubb Meyer & Lovejoy, February 2, 1999: US05867430 (95 worldwide citation)

A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state ma ...


3
Takao Akaogi, Masanobu Yoshida, Yasushige Ogawa, Yasushi Kasa, Shouichi Kawamura: Nonvolatile semiconductor memory. Fujitsu, Nikaido Marmelstein Murray & Oram, December 31, 1996: US05590074 (62 worldwide citation)

A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memor ...


4
Takao Akaogi, Masanobu Yoshida, Yasushige Oqawa, Yasushi Kasa, Shouichi Kawamura: Nonvolatile semiconductor memory. Fujitsu, Nikaido Marmelstein Murray & Oram, July 16, 1996: US05537356 (46 worldwide citation)

When a current flows through a selected memory cell transistor at the time of data reading, the gate voltage of an n-channel MOS transistor, which makes up the current flowing through the load, rises. Thus, when a current flows through a selected memory cell transistor at the time of data reading, t ...


5
Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi Kawashima, Minoru Yamashita: Semiconductor memory device for selecting and deselecting blocks of word lines. Fujitsu, Nikaido Marmelstein Murray & Oram, September 19, 1995: US05452251 (38 worldwide citation)

A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines a ...


6
Takao Akaogi, Hiromi Kawashima, Tetsuji Takeguchi, Ryoji Hagiwara, Yasushi Kasa, Kiyoshi Itano, Yasushige Ogawa, Shouichi Kawamura: Flash memory with improved erasability and its circuitry. Fujitsu, Nikaido Marmelstein Murray & Oram, March 4, 1997: US05608670 (35 worldwide citation)

The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective ...


7
Takao Akaogi, Masanobu Yoshida, Yasushige Ogawa, Yasushi Kasa, Shouichi Kawamura: Nonvolatile semiconductor memory. Fujitsu, Nikaido Marmelstein Murray & Oram, January 23, 1996: US05487036 (35 worldwide citation)

A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memor ...


8
Takao Akaogi, Mitsuo Higuchi: Semiconductor memory device having redundant memory cells. Fujitsu, Armstrong Westerman Hattori McLeland & Naughton, March 23, 1993: US05197030 (28 worldwide citation)

A semiconductor memory device includes a memory cell array, a data readout circuit, a decoder circuit and an address transition detecting circuit which detects an address transition of an input address signal and which generates an address transition detection pulse. A redundancy circuit determines ...


9
Takao Akaogi, Kazuhiro Kurihara, Tien Min Chen: Address transistion detect timing architecture for a simultaneous operation flash memory device. Advanced Micro Devices, Fujitsu, Brinks Hofer Gilson & Lione, August 29, 2000: US06111787 (24 worldwide citation)

An address transition signal generator for a dual bank flash memory device is disclosed. The generator includes signal transition detectors which monitor control signals of the device for transitions in their logical values. Upon detection of a signal transition, the transition detectors send a sign ...


10
Takao Akaogi: Semiconductor memory device. Fujitsu, Armstrong Nikaido Marmelstein Kubovcik & Murray, February 25, 1992: US05091888 (24 worldwide citation)

A semiconductor memory device comprises memory cells for storing data, reference cells for storing reference data, and an output part supplied with an output signal from the memory cells and a reference signal from the reference cells for comparing the output signal and the reference signal and prod ...