1
Hidekazu Matsumoto, Tadaaki Bandoh, Hideo Maejima: Data processing unit with pipelined operands. Hitachi, Antonelli Terry & Wands, June 12, 1984: US04454578 (126 worldwide citation)

A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations is disclosed. An instruction fetch unit includes an instruction buffer for prefetching and retain ...


2
Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin ichi Sinoda: Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices. Hitachi, Antonelli Terry Stout & Kraus, July 21, 1992: US05133064 (116 worldwide citation)

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock ...


3
Yasushi Fukunaga, Tadaaki Bandoh, Hidekazu Matsumoto, Ryosei Hiraoka, Jushi Ide, Takeshi Kato, Tetsuya Kawakami: Shared virtual address translation unit for a multiprocessor system. Hitachi, Hitachi Engineering, Antonelli Terry & Wands, November 6, 1984: US04481573 (110 worldwide citation)

A virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed. One of the plurality of processors is a job processor which accesses the main memory with a virtual address to ex ...


4
Masahiko Saito, Kenichi Kurosawa, Yoshiki Kobayashi, Tadaaki Bandoh, Masahiro Iwamura, Takashi Hotta, Yasuhiro Nakatsuka, Shigeya Tanaka, Takeshi Takemoto: Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory. Hitachi, Antonelli Terry Stout & Kraus, July 21, 1998: US05784630 (65 worldwide citation)

A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of ...


5
Yasushi Fukunaga, Tadaaki Bandoh, Ryosei Hiraoka, Hidekazu Matsumoto, Jushi Ide, Tetsuya Kawakami: Bus selection control in a data transmission apparatus for a multiprocessor system. Hitachi, Hitachi Engineering, Antonelli Terry & Wands, June 11, 1985: US04523272 (63 worldwide citation)

In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferr ...


6
Kenji Hirose, Tadaaki Bandoh, Hidekazu Matsumoto, Shinichiro Yamaguchi, Hirokazu Hirayama, Hiroaki Nakanishi: Apparatus for performing floating point arithmetic operations and rounding the result thereof. Hitachi, Hitachi Engineering, Antonelli Terry & Wands, June 13, 1989: US04839846 (49 worldwide citation)

An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an output of a mantissa shifter and a signal representing round-up, a carry look-ahead circuit and a circui ...


7
Kenji Hirose, Tadaaki Bandoh, Hidekazu Matsumoto, Shinichiro Yamaguchi, Hirokazu Hirayama, Hiroaki Nakanishi: Bit slice multiplication circuit. Hitachi, Hitachi Engineering, Antonelli Terry & Wands, March 7, 1989: US04811269 (49 worldwide citation)

A bit slice multiplication circuit operating to slice a multiplier, produce products for the sliced multipliers and a multiplicand and sum the products to obtain the multiplication result. The circuit includes a slicing unit for slicing the multiplicand, multiplying units corresponding in number to ...


8
Tadaaki Bandoh: Multi-processor system having a multi-port cache memory. Hitachi, Antonelli Terry Stout & Kraus, September 21, 1993: US05247649 (46 worldwide citation)

A multi-port cache memory of multi-port memory structure is connected to and shared with a plurality of processors. The multi-port cache memory may have two sets of interface signal lines, for instruction fetch and for data read/write, to each processor. The multi-port cache memory may also be used ...


9
Yasushi Fukunaga, Tadaaki Bandoh: Data processing system with processors having different processing speeds sharing a common bus. Hitachi, Antonelli Terry & Wands, June 11, 1985: US04523274 (46 worldwide citation)

There is disclosed a data processing system comprising a plurality of processors having different processing speeds and connected with a synchronous common bus, the processors being able to access a common memory connected with the common bus.


10
Yasushi Fukunaga, Tadaaki Bandoh, Kotaro Hirasawa, Hidekazu Matsumoto, Jushi Ide, Takeshi Katoh, Hiroaki Nakanishi, Tetsuya Kawakami, Ryosei Hiraoka: Central processing unit for executing instructions of variable length having end information for operand specifiers. Hitachi, Hitachi Engineering, Antonelli Terry & Wands, July 16, 1985: US04530050 (42 worldwide citation)

A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or ...