1
Taber H Smith, Vikas Mehrotra, David White: Characterization and reduction of variation for integrated circuits. Cadence Design Systems, Bingham McCutchen, June 3, 2008: US07383521 (270 worldwide citation)

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.


2
David White, Taber H Smith: Characterization and verification for integrated circuit designs. Praesagus, Bingham McCutchen, February 6, 2007: US07174520 (253 worldwide citation)

Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process ...


3
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Praesagus, Bingham McCutchen, October 17, 2006: US07124386 (252 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


4
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Praesagus, Fish & Richardson P C, December 19, 2006: US07152215 (239 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


5
David White, Taber H Smith: Adjustment of masks for integrated circuit fabrication. Cadence Design Systems, Bingham McCutchen, April 29, 2008: US07367008 (205 worldwide citation)

A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch pro ...


6
Taber H Smith, Vikas Mehrotra, David White: Use of models in integrated circuit fabrication. Cadence Design Systems, Bingham McCutchen, April 15, 2008: US07360179 (193 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


7
David White, Taber H Smith: Test masks for lithographic and etch processes. Praesagus, Bingham McCutchen, July 10, 2007: US07243316 (188 worldwide citation)

A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated ...


8
David White, Taber H Smith: Characterization and verification for integrated circuit designs. Cadence Design Systems, Vista IP Law Group, May 4, 2010: US07712056 (156 worldwide citation)

Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process ...


9
David White, Taber H Smith: Electronic design for integrated circuits based on process related variations. Cadence Design Systems, Vista IP Law Group, June 14, 2011: US07962867 (154 worldwide citation)

An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on ...


10
Taber H Smith, Vikas Mehrotra, David White: Characterization and reduction of variation for integrated circuits. Cadence Design Systems, Vista IP Law Group, August 16, 2011: US08001516 (51 worldwide citation)

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.



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