1
Ai Min Tan, Gerald Ofner, Swain Hong Yeo, Mary Teo, Pei Siang Lim: Magnetically alignable integrated circuit device. Infineon Technologies, Dicke Billig & Czaja PLLC, August 9, 2011: US07994608 (9 worldwide citation)

An integrated circuit device includes a semiconductor chip having an active surface with a plurality of chip contact pads, a rewiring substrate and an electrically conductive inductor coil for magnetically aligning the semiconductor chip with the rewiring substrate.


2
Gerald Ofner, Swain Hong Yeo, Mary Teo, Pei Siang Lim, Khoon Lam Chua: Integrated circuit package and a method for forming an integrated circuit package. Infinenon Technologies, Slater & Matsil L, January 22, 2013: US08357565 (4 worldwide citation)

A method of forming an integrated circuit package, such as a Flip Chip package, in which a void is provided in the underfill material in the central region of the package between the chip or die and the substrate on which the chip or die is mounted. This reduces delamination of the package as a resu ...


3
Alfred Swain Hong Yeo: Three-dimensional stack of leaded package and electronic member. Infineon Technologies, July 4, 2017: US09698083

An electronic device comprising a package comprising an encapsulated electronic chip, at least one at least partially exposed electrically conductive carrier lead for mounting the package on and electrically connecting the electronic chip to a carrier, and at least one at least partially exposed ele ...


4
Ai Min Tan, Gerald Ofner, Swain Hong Yeo, Mary Teo, Pei Siang Lim: Magnetically Alignable Integrated Circuit Device. Infineon Technologies, Dicke Billig & Czaja, October 30, 2008: US20080265367-A1

An integrated circuit device includes a semiconductor chip having an active surface with a plurality of chip contact pads, a rewiring substrate and an electrically conductive inductor coil for magnetically aligning the semiconductor chip with the rewiring substrate.


5
Irwin Aberin, Gerald Ofner, Alfred Swain Hong Yeo, Wen Hui Zhu: Semiconductor Package with Perforated Substrate. Dicke Billig & Czaja, June 26, 2008: US20080150159-A1

A semiconductor package includes a substrate and a semiconductor chip which includes an active surface with a plurality of chip contact areas. The chip is electrically connected to the substrate. The substrate includes a sheet of core material, a plurality of upper conducting traces and upper contac ...


6
Gerald Ofner, Swain Hong Yeo, Mary Teo, Pei Siang Lim, Khoon Lam Chua: Integrated Circuit Package and a Method for Forming an Integrated Circuit Package. Slater & Matsil, May 29, 2008: US20080122053-A1

A method of forming an integrated circuit package, such as a Flip Chip package, in which a void is provided in the underfill material in the central region of the package between the chip or die and the substrate on which the chip or die is mounted. This reduces delamination of the package as a resu ...


7
Gerald OFNER, Swain Hong YEO, Mary TEO, Pei Siang LIM, Khoon Lam CHUA: Integrated Circuit Package and a Method for Forming an Integrated Circuit Package. OFNER Gerald, January 27, 2011: US20110020985-A1

A method of forming an integrated circuit package, such as a Flip Chip package, in which a void is provided in the underfill material in the central region of the package between the chip or die and the substrate on which the chip or die is mounted. This reduces delamination of the package as a resu ...