1
Haoran Duan, John W Lockwood, Sung Mo Kang: Scalable broad band input-queued ATM switch including weight driven cell scheduler. Board of Trustees of the University of Illinois, Greer Burns & Crain, July 13, 1999: US05923656 (54 worldwide citation)

An asynchronous mode transfer (ATM) switch conducting switching based upon the calculation of weights for entries corresponding to cells in an input queue to achieve a high throughput rate which avoids head of line blocking. The switch includes a cell scheduler driven by the iterative resolution of ...


2
Sung Mo Kang, Seung Moon Yoo: Low-power high-performance integrated circuit and related methods. The Regents of the University of California, Morrison & Foerster, March 13, 2007: US07190209 (31 worldwide citation)

An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is tur ...


3
Carlos H Diaz, Charvaka Duvvury, Sung Mo Kang: ESD/EOS protection circuits for integrated circuits. Texas Instruments Incorporated, Jacqueline J Garner, Richard L Donaldson, William E Hiller, September 12, 1995: US05450267 (25 worldwide citation)

An ESD/EOS protection circuit 10. Trigger nMOS transistor M1 has a drain 20 connected to a voltage pad 22, a gate 24 connected to ground 26 and a source 28 connected to ground 26 through source resistor R.sub.e. Switch control nMOS transistor M2 has a drain 30, a gate 34 connected to source 28 of tr ...


4
Chulwoo Kim, Sung Mo Kang: Delay locked loop clock generator. The Board of Trustees of the University of Illinois, Greer Burns & Crain, August 31, 2004: US06784707 (21 worldwide citation)

A delay locked loop (DLL) clock generator circuit is provided for generating a clock signal Clk according to a pair of input signals to the circuit. One of the input signals is a reference signal, and the second input signal is a feedback signal of a voltage controlled delay line circuit. The DLL ci ...


5
Sung Mo Kang, Seung Moon Yoo: Low-power high-performance storage circuitry. The Regents of the University of California, Morrison & Foerster, May 3, 2005: US06888202 (20 worldwide citation)

An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transis ...


6
Carlos H Diaz, Charvaka Duvvury, Sung Mo Kang: Method of placing source contacts for efficient ESD/EOS protection in grounded substrate MOS integrated circuit. Texas Instruments Incorporated, Jacqueline J Garner, Richard L Donaldson, William E Hiller, November 21, 1995: US05468667 (19 worldwide citation)

An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A first metal layer (162) substantially covers e ...


7
Carlos H Diaz, Charvaka Duvvury, Sung Mo Kang: Source contact placement for efficient ESD/EOS protection in grounded substrate MOS integrated circuit. Texas Instruments Incorporated, Jacqueline J Garner, Richard L Donaldson, William E Hiller, April 4, 1995: US05404041 (19 worldwide citation)

An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A first metal layer (162) substantially covers e ...


8
Sung Mo Kang, Seung Moon Yoo: Reverse biasing logic circuit. The Board of Trustees of the University of Illinois, Greer Burns & Crain, July 6, 2004: US06759873 (15 worldwide citation)

A reverse biasing logic circuit is disclosed for limiting standby leakage electric current losses during circuit operation. The circuit includes a logic function circuit having one or more logic transistors that receive an input and perform a logic function operation to generate an output. A power s ...


9
Sung Mo Kang, Seung Moon Yoo: Event driven dynamic logic for reducing power consumption. The Regents of the University of California, John P O Banion, December 20, 2005: US06977528 (14 worldwide citation)

Methods and circuits are described for reducing power consumption within digital logic circuits by blocking the passage of clock signal transitions to the logic circuits when the clock signal would not produce a desired change of state within the logic circuit, such as at inputs, intermediary nodes, ...


10
Duk Rae Kim, Sung Mo Kang: Switching mechanism of circuit breaker for gas insulted switchgear. LG Industrial Systems, Greenblum & Bernstein, September 7, 2004: US06787725 (11 worldwide citation)

A switching mechanism of a circuit breaker for a gas insulated switchgear is able to extinguish arc gas by changing a volume of a compressing chamber without increasing a stroke of a movable cylinder and without increasing required output power of an actuator.