1
Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou: Method of making multichip wafer level packages and computing systems incorporating same. Micron Technology, TraskBritt, February 3, 2009: US07485562 (94 worldwide citation)

The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layer ...


2
Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou: Multi-chip wafer level system packages and methods of forming same. Micron Technology, TraskBritt, November 15, 2005: US06964881 (22 worldwide citation)

The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die are contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect l ...


3
Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang: Multiple chip semiconductor package and method of fabricating same. Micron Technology, TraskBritt, January 17, 2006: US06987031 (15 worldwide citation)

A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as ...


4
Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou: Multichip wafer level packages and computing systems incorporating same. Micron Technology, TraskBritt, November 30, 2004: US06825553 (13 worldwide citation)

The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layer ...


5
Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang: Multiple chip semiconductor package. Micron Technology, TraskBritt, October 25, 2005: US06958537 (12 worldwide citation)

A semiconductor device package is disclosed. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip tec ...


6
Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang: Multiple chip semiconductor package. Micron Technology, TraskBritt, February 6, 2007: US07173330 (10 worldwide citation)

A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as ...


7
Swee Kwang Chua, Siu Waf Low, Yong Poo Chia, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Suangwu Huang, Wei Zhou: Multichip wafer level packages and computing systems incorporating same. Micron Technology, TraskBritt PC, August 8, 2006: US07087992 (8 worldwide citation)

The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layer ...


8
Meow Koon Eng, Yong Poo Chia, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua, Suangwu Huang: Multiple chip semiconductor package. Micron Technology, TraskBritt, June 30, 2009: US07553697 (1 worldwide citation)

A semiconductor device package and method of fabricating the same are disclosed. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace ...