1
Christopher Paul Miller, Jim Lewis Rogers, Steven William Tomashot: Cached synchronous DRAM architecture allowing concurrent DRAM operations. International Business Machines Corporation, Robert A Walsh, July 28, 1998: US05787457 (145 worldwide citation)

A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture includes a synchronous dynamic random access memory (SDRAM) bank including a row decoder coupled to a memory bank array for selecting a row of data in the memory bank array, sense amplifiers coup ...


2
Claude Louis Bertin, John A Fifield, Erik Leigh Hedberg, Russell J Houghton, Timothy Dooling Sullivan, Steven William Tomashot, William Robert Tonti: Impedance control using fuses. International Business Machines Corporation, Howard J Walker Jr esq, Scully Scott Murphy & Presser, October 31, 2000: US06141245 (65 worldwide citation)

A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective devi ...


3
William Paul Hovis, Steven William Tomashot: Clocked memory device that includes a programming mechanism for setting write recovery time as a function of the input clock. International Business Machines Corporation, Derek P Martin, Martin & Associates L L C, August 13, 2002: US06434082 (20 worldwide citation)

A clocked memory device includes a programming mechanism that allows the write recovery time during a command with auto precharge enabled to be dynamically set to some function of the input clock. In the preferred embodiments, the programming mechanism includes a control register with programmable b ...


4
Michael William Curtis, William Paul Hovis, Steven William Tomashot: Multiple memory bank command for synchronous DRAMs. International Business Machines Corporation, Karuna Ojanen, August 20, 2002: US06438062 (20 worldwide citation)

An improved and much simplified method to access data banks in a memory system which provides the option of opening more than one bank in a single command. This is especially useful to achieve bursts of data across bank boundaries in a memory system of synchronous dynamic random access memory cards ...


5
Claude Louis Bertin, John A Fifield, Erik Leigh Hedberg, Russell J Houghton, Timothy Dooling Sullivan, Steven William Tomashot, William Robert Tonti: Impedance control using fuses. International Business Machines Corporation, Howard J Walter Jr Esq, Scully Scott Murphy & Presser, June 5, 2001: US06243283 (16 worldwide citation)

A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective devi ...


6
Dale Edward Pontius, Steven William Tomashot, Toshiaki Kirihata, Robert Henry Kruggel: Address transition detector (ATD) for power conservation. International Business Machines Corporation, Howard J Walter Jr, Whitham Curtis Whitham & McGinn, April 28, 1998: US05745431 (5 worldwide citation)

An address decode circuit for receiving address input signals, includes a device for detecting a change in the address input signals, and a device for generating a control signal in response to a detected change in the address input signals. A gating mechanism gates at least one address bit in the a ...


7
Nathan Rafael Hiltebeitel, Robert Tamlyn, Steven William Tomashot, Thomas Walter Wyckoff: Redundancy architecture and method for block write access cycles permitting defective memory line replacement. International Business Machines Corporation, Mark F Chadurjian, Robert A Walsh, May 4, 1999: US05901093 (4 worldwide citation)

An invention is disclosed which implements bit line redundancy in a memory module, such as a dynamic random access memory (DRAM), in accordance with a block write operation. The block write operation is commonly used in dual port RAMs, sometimes referred to as video random access memories (VRAM). Sp ...


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Christopher Paul Miller, Jim Louis Rogers, Steven William Tomashot: Cache synchronous dram architecture enabling parallel dram operation. Internatl Business Mach Corp &Lt IBM&Gt, August 7, 1998: JP1998-208471

PROBLEM TO BE SOLVED: To improve the performance of an SDRAM by a method wherein the waiting time of a memory is reduced and the simultaneous operations in a same memory bank is made to be performed. SOLUTION: In a cache synchronous dynamic random access memory(SDRAM) device having a multibank archi ...


10
Hovis William Paul, Steven William Tomashot: Clocked memory device containing programming mechanisms for setting write recovery time as function of input clock. Internatl Business Mach Corp &Lt IBM&Gt, November 8, 2002: JP2002-324399

PROBLEM TO BE SOLVED: To provide a clocked memory device that contains programming mechanisms to set a write recovery time as a function of input clocks.SOLUTION: The clocked memory device contains programming mechanisms that permit setting the write recovery time dynamically as some function of inp ...